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XRT83SL34 Datasheet(PDF) 14 Page - Exar Corporation |
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XRT83SL34 Datasheet(HTML) 14 Page - Exar Corporation |
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14 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.8 PRELIMINARY 11 JITTER ATTENUATOR SIGNAL NAME PIN #TYPE DESCRIPTION JASEL0 JASEL1 A[6] A[5] 58 57 57 58 I Jitter Attenuator Select Pins - Hardware Mode Jitter Attenuator select pin 0 Jitter Attenuator select pin 1 JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive path or to disable it. Microprocessor Address Bits A[6:5] -Host Mode See “Microprocessor Address Pins - Host mode:” on page 10. NOTE: Internally pulled “Low” with a 50k Ω resistor. Disabled Transmit Receive Receive JA Path JA BW MHz T1/E1 32/32 32/32 64/64 FIFO Size T1 3 3 3 E1 10 10 1.5 0 0 0 0 JASEL1 0 0 1 1 JASEL0 Disabled Transmit Receive Receive JA Path JA BW Hz -------- 32/32 32/32 64/64 FIFO Size ----- 3 3 3 ----- 10 10 1.5 0 0 1 1 JASEL1 0 1 0 1 JASEL0 T1 E1 |
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