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XRT83SL34 Datasheet(PDF) 33 Page - Exar Corporation |
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XRT83SL34 Datasheet(HTML) 33 Page - Exar Corporation |
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33 / 80 page ![]() XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.0.8 30 diagram for T1 (100 Ω) in the external termination mode. Figure 13 is a simplified block diagram for E1 (75Ω) in the external termination mode. Table 11 summarizes the transmit terminations. REDUNDANCY APPLICATIONS Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without losing data. System designers can achieve this by implementing common redundancy schemes with the XRT83SL34 Line Interface Unit (LIU). The XRT83SL34 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. These features allow system designers to implement redundancy applications that ensure reliability. The Internal Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy schemes. TABLE 10: TRANSMIT TERMINATION CONTROL TRATIO TURNS RATIO 01:2.45 11:2 TABLE 11: TRANSMIT TERMINATIONS TERSEL1 TERSEL0 TXTSEL TRATIO Rint Ω n Rext Ω Cext 0=EXTERNAL SET BY CONTROL BITS n, Rext, AND Cext ARE SUGGESTED SETTINGS 1=INTERNAL T1 100 Ω 0 000 0 Ω 2.45 3.1 Ω 0 0 001 0 Ω 23.1 Ω 0 0 0 1 x 12.5 Ω 20 Ω 0.68 µF J1 110 Ω 0 100 0 Ω 2.45 3.1 Ω 0 0 101 0 Ω 23.1 Ω 0 0 1 1 x 13.75 Ω 20 Ω 0.68 µF E1 75 Ω 1 000 0 Ω 2.45 6.2 Ω 0 1 001 0 Ω 29.1 Ω 0 10 1 x 9.4 Ω 20 Ω 0.68 µF E1 120 Ω 1 100 0 Ω 2.45 6.2 Ω 0 1 101 0 Ω 29.1 Ω 0 11 1 x 15 Ω 20 Ω 0.68 µF |
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