AD9546SLASHPCBZ datasheet(174/205 Pages) AD

174 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 174 of 205

Use the following formulas to verify the register value

computations, Cxʹ, closely match the desired coefficient value:

C0ʹ = C0_RegVal × 2−45

(27)

2 xE

x S

−

≠

′

(28)

Note that there may be a slight difference between the values

produced by Equation 27 and Equation 28 and the original

coefficient values (Cx) due to quantization effects.

An example of coefficient verification follows:

C0ʹ = 35,349,513,305 × 2−45

= 1.004694 × 10−3 (compare: C0 = 1.0046936 × 10−3)

C1ʹ = −24,849 × 2−18 − 15

= −2.892804 × 10−6 (compare: C1 = −2.8927765 × 10−6)

C2ʹ = −26,265 × 2−22 − 15

= −1.911030 × 10−14 (compare: C2 = −1.9110192 × 10−7)

C3ʹ = 19,786 × 2−28 − 15

= 2.249408 × 10−9 (compare: C3 = 2.2493907 × 10−9)

C4ʹ = 31,462 × 2−35 − 15

= 2.794387 × 10−11 (compare: C4 = 2.7943570 × 10−11)

C5ʹ = −17,883 × 2−41 − 15

= −2.481765 × 10−13 (compare: C5 = −2.4817310 × 10−13)

Digital Filter

The CF1 values produced by the polynomial calculator block in

Figure 116 depend on temperature measurements (internal or

external) as an input parameter. Any noise associated with

those measurements is a potential noise source on CF1, which

can lead to a degradation of phase noise performance. To

mitigate potential noise injection by the compensation

mechanism, Compensation Method 1 employs a filter that

applies a smoothing function to the raw CF1 values.

The user controls the filter bandwidth via Bits[2:0] of

collocated poles that yield a 3 dB bandwidth per Table 98.

Table 98. Digital Filter Bandwidth

Bits[2:0] (Binary)

3 dB Bandwidth (Hz)

000

156

001

010

011

100

101

110

111

The AD9546 automatically bypasses the digital filter under the

following conditions:

•

The system clock is unstable.

•

The difference between the input and output of the digital

filter exceeds ~125 ppm.

None of these conditions occurs during normal operation.

Thus, the filter is nearly always present.

COMPENSATION METHOD 2

Compensation Method 2 employs the closed-loop method of

system clock compensation (see the Closed-Loop Method section).

As shown in Figure 118, Compensation Method 2 makes use of

one of the DPLLx channels (where x is 0 or 1). The user must

specify which DPLL to use via Bit 0 of Register 0x0287. Logic 0

(default) selects DPLL0, and Logic 1 selects DPLL1 as the source of

CF2. CF2 embodies the factor, 1 + FFECOMP, in Figure 115.

Compensation Method 2 generates the correction factor, CF2,

which the user can apply to other NCOs and TDCs within the

AD9546. However, a compensation factor, COMPx, can be applied

to the NCO of DPLLx in Figure 118. Because it is possible for the

COMPx factor to include CF2 (see the Integrated Compensation

Subsystem section for details), the user must ensure that the NCO

of the DPLL channel selected for Compensation Method 2 is not

itself a recipient of CF2 via COMPx.

XOA

XOB

SYSTEM

CLOCK

SOURCE

fSRC

AD9546

FTW

STABLE

FREQUENCY

SOURCE

FTW

ANALYZER

DPLLx

fREF

fNCO

CF2

FROM

FEEDBACK

TDC

REFERENCE

DIVIDER

AND TDC

COMPx

DIGITAL

PFD AND

LOOP

FILTER

NCO

SYSTEM

CLOCK PLL

Figure 118. Compensation Method Number 2

AD9546/PCBZ Datasheet(PDF) 174 Page - Analog Devices

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