AD9546SLASHPCBZ datasheet(176/205 Pages) AD

176 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 176 of 205

The auxiliary DPLL reference monitor status is also available

via the IRQ mechanism (see the Interrupt Request (IRQ)

section) by means of Bit 2 and Bit 3 of Register 0x300C. Bit 2

and Bit 3 provide latched information regarding state

transitions of the auxiliary DPLL reference status bit. Bit 2

latches to Logic 1 when the auxiliary DPLL reference status bit

transitions from Logic 0 to Logic 1, whereas Bit 3 latches to

Logic 1 when the auxiliary DPLL reference status bit transitions

from Logic 1 to Logic 0.

Because Bit 2 and Bit 3 represent the latched state transitions of

the auxiliary DPLL reference status bit, they may represent a

condition that is no longer true. Therefore, the user must clear

Bit 2 and Bit 3 via Bit 2 and Bit 3, respectively, of Register 0x2007.

Otherwise, the user may lose indication of subsequent state

changes of the auxiliary DPLL reference status bit.

XOA

XOB

SYSTEM

CLOCK

SOURCE

fSRC

AD9546

TIME STAMP

PROCESSOR

AUXILIARY DPLL

REFERENCE

MONITOR

LOCK

DETECTOR

DIGITAL

LOOP

FILTER

REFx

OR Mx

STABLE

FREQUENCY

SOURCE

fREF

REFERENCE

DIVIDER

AND TDC

DIGITAL

CROSS

POINT

MUX

TIME

STAMPS

PROGRAMMED

REFERENCE

PERIOD

REFERENCE

SOURCE

SELECT

PERIOD

ERROR

TIME SCALE

GENERATOR

REG 0x0206 TO 0x0202, BITS[39:0]

SYSCLK REF FREQ

CF3

SYSTEM CLOCK

COMPENSATION

SUBSYSTEM

INTERFACE

COMPX

TIME

SCALE

NOTE

1. A RANGE OF BITS USES A COLON SEPARATOR

SYSTEM

CLOCK PLL

REG 0x0286 TO 0x0285, BITS[15:0]

REG 0x0284, BITS[4:0]

REG 0x040B TO 0x0404, BITS[59:0]

REG 0x042B TO 0x0424, BITS[59:0]

REG 0x044B TO 0x0444, BITS[59:0]

REG 0x046B TO 0x0464, BITS[59:0]

REG 0x048B TO 0x0484, BITS[59:0]

REG 0x04AB TO 0x04A4, BITS[59:0]

REG 0x04CB TO 0x04C4, BITS[59:0]

REG 0x04EB TO 0x04E4, BITS[59:0]

Figure 119. Compensation Method 3

AD9546/PCBZ Datasheet(PDF) 176 Page - Analog Devices

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