AD9546SLASHPCBZ datasheet(175/205 Pages) AD

175 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 175 of 205

COMPENSATION METHOD 3

Compensation Method 3 is unavailable in digitized clocking

applications (see the Common Clock DPLL section).

Compensation Method 3 employs the closed-loop method of

system clock compensation (see the Closed-Loop Method

section). As shown in Figure 119, Compensation Method 3

produces correction factor CF3, where CF3 embodies the factor,

1 + FFECOMP, in Figure 115. Compensation Method 3 and

Compensation Method 2 are similar, but Compensation

Method 3 uses the auxiliary DPLL rather than one of the DPLL

channels. Because Compensation Method 3 relies on the

availability of a stable external clock source applied to one of

the REFx inputs or one of the auxiliary REFx inputs (via an Mx

pin), the user must assign the TDC associated with the external

clock source to the auxiliary DPLL via Bits[4:0] of

various TDCs.

Table 99. Auxiliary DPLL TDC Assignment Codes

Bits[4:0] (Decimal)

TDC Description

REFA TDC (default)

REFAA TDC

REFB TDC

4 to 5

Unused

Auxiliary REF0 TDC

Auxiliary REF1 TDC

8 to 10

Unused

Auxiliary REF2 TDC

Auxiliary REF3 TDC

13 to 15

Unused

The auxiliary DPLL can itself receive compensation from other

sources via COMPx in Figure 119 (see the Integrated

Compensation Subsystem section for details). Unlike

Compensation Method 2, the CF3 compensation factor does

not include the contribution of COMPx. That is, CF3 comprises

only the residual error to represent the frequency deviation

associated with the system clock source only.

Assuming the auxiliary DPLL is locked and has fully settled, the

period of the stable reference must exactly match the

programmed reference period stored in the register associated

with the selected reference (see Figure 119). Any deviation is an

indication of error associated with the system clock period and

leads to a corresponding CF3 value. There are two error

sources: stability error and accuracy error.

Stability error involves deviation from the mean value over

time (the mean corresponding to a specific operating condition

like 25°C, for example). As temperature varies over time, the

frequency of the oscillator serving as the source for the system

clock varies in response to the temperature changes. Given the

prerequisite that the stable reference is significantly more stable

than the system clock source, the dominant variations

appearing in the feedback path are those of the system clock.

Because the system clock variations are the dominant

contributor to CF3, CF3 reflects the corrections necessary to

compensate for the temperature induced stability errors on the

system clock.

Accuracy error is the difference between the defined nominal

frequency and the actual frequency. The defined nominal

frequency derives from programmed reference period stored in

the register associated with the selected reference. The actual

frequency is fREF, the true frequency of the stable reference (see

Figure 119). The accuracy error is the difference between the

programmed reference period and the actual nominal period of

the stable reference (1/fREF).

Because CF3 is a composite of both the stability and accuracy

error sources, the programmed reference period directly affects

the accuracy error component of CF3. Thus, accurate entry of

the stable reference clock period is crucial, because the accuracy

error propagates to any COMPx involving CF3 (see the

Integrated Compensation Subsystem section).

Auxiliary DPLL Loop Bandwidth

The user controls the loop bandwidth of the auxiliary DPLL

servo loop (BWCOMP) via Bits[15:0] (unsigned) in

scaled by the 16-bit decimal value of Bits[15:0].

For example, given a desired value of BWCOMP = 247.63 Hz,

determine the appropriate value of Bits[15:0] as follows:

Bits[15:0] = BWCOMP/0.1

= 247.63/0.1 Hz

= 2476 (nearest integer)

= 0x 09AC (hexadecimal)

The programmed bandwidth affects how long it takes the

auxiliary DPLL to lock to the stable reference: a lower

bandwidth means it takes the auxiliary DPLL longer to lock.

The programmed bandwidth also affects the ability of the

auxiliary DPLL to track variations in the frequency (fS) of the

system clock. Specifically, a relatively stable, slowly varying

system clock frequency allows the use of a low loop bandwidth,

whereas a system clock exhibiting more rapid frequency

variations requires a wider loop bandwidth. For example, using

an OCXO as the system clock reference allows the use of a

0.1 Hz loop bandwidth, whereas a standard crystal oscillator

necessitates a loop bandwidth in excess of 50 Hz.

Auxiliary DPLL Reference Monitor Status

The auxiliary DPLL has a dedicated reference monitor to

provide indication that the reference period is within limits.

The reference monitor relies on the defined reference period

(user input via the appropriate registers).

The auxiliary DPLL reference monitor status is available in real

time via Bit 2 (auxiliary DPLL reference status) of

states are Logic 1 and Logic 0, respectively.

AD9546/PCBZ Datasheet(PDF) 175 Page - Analog Devices

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