STM32G030C6 datasheet(18/94 Pages) STMICROELECTRONICS

18 / 94 page

Functional overview

STM32G030x6/x8

18/94

DS12991 Rev 4

3.9

Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:

•

Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

•

Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

•

Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

•

System clock source: three different sources can deliver SYSCLK system clock:

–

4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

–

16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

–

System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

•

Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

–

32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

–

32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

•

Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, ADC) have their

own clock independent of the system clock.

•

Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

CPU (hard fault)

TIM1,16,17

Timer break

GPIO

TIMx

External trigger

ADC

Conversion external trigger

Table 4. Interconnect of peripherals (continued)

Interconnect source

Interconnect

destination

Interconnect action

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