STM32H7B3AI datasheet(235/238 Pages) STMICROELECTRONICS

235 / 238 page

List of figures

Figure 1.

STM32H7B3xI block diagram ......................................................... 11

Figure 2.

Power-up/power-down sequence ...................................................... 15

Figure 3.

STM32H7B3xI bus matrix ........................................................... 19

Figure 4.

LQFP64 (STM32H7B3xI without SMPS) pinout............................................. 36

Figure 5.

LQFP100 (STM32H7B3xI with SMPS) pinout .............................................. 37

Figure 6.

LQFP100 (STM32H7B3xI without SMPS) pinout ............................................ 38

Figure 7.

TFBGA100 (STM32H7B3xI with SMPS) pinout ............................................. 39

Figure 8.

TFBGA100 (STM32H7B3xI without SMPS) pinout........................................... 39

Figure 9.

WLCSP132 (STM32H7B3xI with SMPS) ballout ............................................ 40

Figure 10.

LQFP144 (STM32H7B3xI with SMPS) pinout .............................................. 41

Figure 11.

LQFP144 (STM32H7B3xI without SMPS) pinout ............................................ 42

Figure 12.

LQFP176 (STM32H7B3xI with SMPS) pinout .............................................. 43

Figure 13.

LQFP176 (STM32H7B3xI without SMPS) pinout ............................................ 44

Figure 14.

TFBGA216 (STM32H7B3xI without SMPS) ballout .......................................... 45

Figure 15.

TFBGA225 (STM32H7B3xI with SMPS) ballout ............................................ 46

Figure 16.

UFBGA169 (STM32H7B3xI with SMPS) ballout ............................................ 46

Figure 17.

UFBGA176+25 (STM32H7B3xI with SMPS) ballout.......................................... 47

Figure 18.

UFBGA176+25 (STM32H7B3xI without SMPS) ballout ....................................... 48

Figure 19.

Pin loading conditions .............................................................. 79

Figure 20.

Pin input voltage .................................................................. 79

Figure 21.

Power supply scheme .............................................................. 80

Figure 22.

Current consumption measurement scheme............................................... 81

Figure 23.

External capacitor CEXT ............................................................. 86

Figure 24.

SMPS efficicency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, TJ = 30 °C......... 88

Figure 25.

SMPS efficiency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, TJ = 130 °C ........ 88

Figure 26.

SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 30 °C .. 89

Figure 27.

SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 130 °C . 89

Figure 28.

SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 30 °C . 90

Figure 29.

SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 130 °C. 90

Figure 30.

High-speed external clock source AC timing diagram........................................ 107

Figure 31.

Low-speed external clock source AC timing diagram ........................................ 108

Figure 32.

Typical application with an 8 MHz crystal ................................................ 109

Figure 33.

Typical application with a 32.768 kHz crystal ..............................................110

Figure 34.

VIL/VIH for all I/Os except BOOT0 ......................................................118

Figure 35.

Recommended NRST pin protection ................................................... 123

Figure 36.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms ............................ 124

Figure 37.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms ............................ 126

Figure 38.

Asynchronous multiplexed PSRAM/NOR read waveforms .................................... 127

Figure 39.

Synchronous multiplexed NOR/PSRAM read timings........................................ 130

Figure 40.

Synchronous multiplexed PSRAM write timings ........................................... 131

Figure 41.

Synchronous non-multiplexed NOR/PSRAM read timings .................................... 133

Figure 42.

Synchronous non-multiplexed PSRAM write timings ........................................ 134

Figure 43.

NAND controller waveforms for read access.............................................. 135

Figure 44.

NAND controller waveforms for write access ............................................. 136

Figure 45.

NAND controller waveforms for common memory read access ................................. 136

Figure 46.

NAND controller waveforms for common memory write access ................................. 137

Figure 47.

SDRAM read access waveforms (CL = 1) ............................................... 138

Figure 48.

SDRAM write access waveforms ..................................................... 139

Figure 49.

OctoSPI timing diagram - SDR mode................................................... 142

Figure 50.

OctoSPI timing diagram - DTR mode................................................... 143

Figure 51.

OctoSPI Hyperbus clock ........................................................... 143

Figure 52.

OctoSPI Hyperbus read ............................................................ 143

STM32H7B3xI

List of figures

DS13139 - Rev 8

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