EB632 datasheet(43/112 Pages) FREESCALE

43 / 112 page

CPM

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

delineation state machine

— Payload descrambling using self synchronizing scrambler (programmable by the user)

— Coset removing (programmable by the user)

— Filtering idle/unassigned cells (programmable by the user)

— Performing HEC error detection and single bit error correction (programmable by the user)

— Generating loss of cell delineation status/interrupt (LOC / LCD)

•

Serial loop back mode

•

Cell echo mode

•

Supports both FCC transmit modes:

— External rate mode—Idle cells are generated by the FCC (microcode) to control data rate

— Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate. The TC layer

generates idle/unassigned cells to maintain the line bit rate

•

Supports the TC layer and PMD (physical medium dependant) WIRE interface (according to the ATM-Forum

af-phy-0063.000)

14.4.2 ATM TC Layer Support

The MSC8103 supports applications that receive ATM traffic over the standard serial protocols like E1, T1, and

xDSL via its serial interface (SIx TDMx and NMSI) ports because the ATM TC-layer functionality is implemented

internally. This allows the use of standard low-cost PHY devices in system applications instead of PHYs that

support UTOPIA bus devices. A typical TC layer application requires the use of one SI TDM channel per TC

block.

As shown in Figure 14, all TC blocks are internally connected to FCC2. In addition, Figure 14 shows FCC1

connected to a UTOPIA 8-bit MPHY bus that can be routed outside and operated independently from the TC block

Figure 14. Serial ATM Interface Using FCC2 and TC blocks (single channel)

FCC2

FCC1

UTOPIA level-2 8-bit bus

DPR

TDMx

FCC3

SIx

UTOPIA level-2 8-bit bus

Blocks

EB632 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc