EB632 datasheet(63/112 Pages) FREESCALE

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Errata

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

CPM11

False Indication of Shared Flag

Date Added: 5/30/2000

Description: FCC-TX HDLC - FCT_TXD (data out) changes from 1-->0 for 1 ser_clock period,

few clocks after the reset command from MAIN is given. A false shared flag can be detected at

the receiver if the last bit before reset was 0, and the receiver considers it as a closing flag of the

frame. In most of cases, a CRC error is generated and the frame is discarded.

Workaround: None

System Number: 3024

0K40A

1K42A

2K42A

CPM13

Error in Random Number Generation

Date Added: 5/30/2000

Description: In Fast Ethernet transmit, when more then one (up to four) frames reside in the FCC

FIFO, random number generation (for collision wait) may produce the same number for all four

frames.

Workaround: None

System Number: 3421

0K40A

1K42A

2K42A

CPM14

Corruption of ATM Cells

Date Added: 5/30/2000

Description: Corruption of ATM cells may occur when the following combination is used:

AAL1 with UDC in which the user-defined header size is 9 to 12 octets and PM is not used.

Workaround: Since this problem appears in a very specific condition as described above, avoid-

ing any of the elements (e.g., using cell header of 8 octets) eliminates it.

0K40A

1K42A

2K42A

CPM15

Corruption of Port D Registers

Date Added: 5/30/2000

Description: The PDATA, PDATB, PDATC, and PDATD registers can only be written with a

32-bit write instruction. (i.e., stw). When 8- or 16-bit write instructions (i.e., sth, stb) are used, the

bits not being written may be corrupted.

Workaround: Use a 32-bit write instruction only to write to the PDATA, PDATB, PDATC, and

PDATD registers.

System Number: 3679

0K40A

1K42A

2K42A

CPM17

Error in Reporting UTOPIA Error Condition

Date Added: 5/30/2000

Description: An FCC receiver which is configured as single PHY master does not detect a UTO-

PIA error condition when SOC and CLAV are not asserted simultaneously.

System Number: 3728

0K40A

1K42A

2K42A

CPM21

False Indication of Collision in Fast Ethernet

Date Added: 5/30/2000

Description: In the Fast Ethernet a false COL is reported whenever a collision occurs on the pre-

amble of the previous frame.

Workaround: S/W should ignore COL indications when the CRC of the frame is correct.

System Number: 3927

0K40A

1K42A

2K42A

Table 48. Errata Resolved in Mask Set 2K87M (Continued)

Errata

Number

Errata Description

Applies

to Mask

EB632 Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc

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