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AD5671R Datasheet(PDF) 6 Page - Analog Devices

No. de pieza AD5671R
Descripción Electrónicos  16-Channel, 12-/16-Bit nanoDAC with 2 ppm/°C Voltage Reference Temperature Coefficient, SPI Interface
PDF  32 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD5671R Datasheet(HTML) 6 Page - Analog Devices

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AD5674/AD5674R/AD5679/AD5679R
Data Sheet
Rev. B | Page 6 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE OUTPUT
AD5679R-1; AD5679R-2
Output Voltage5
2.4975
2.5025
V
Voltage Reference TC6, 7
2
5
ppm/°C
See the Terminology section
Output Impedance
0.04
Output Voltage Noise
13
µV p-p
0.1 Hz to 10 Hz
Output Voltage Noise Density
240
nV/√Hz
At TA, f = 10 kHz, CL = 10 nF, gain = 1 or 2
Load Regulation Sourcing
29
µV/mA
At ambient temperature
Load Regulation Sinking
74
µV/mA
At ambient temperature
Output Current Load Capability
±20
mA
VDD ≥ 3 V
Line Regulation
43
µV/V
At ambient temperature
Long-Term Stability Drift
77
ppm
After 1000 hours at 25°C
Thermal Hysteresis
125
ppm
First cycle
25
ppm
Additional cycles
LOGIC INPUTS
Input Current
±1
µA
Per pin
VIN
VINL
0.3 × VLOGIC
V
VINH
0.7 ×
VLOGIC
V
Pin Capacitance
4
pF
LOGIC OUTPUTS (SDO)
VOUT
VOL
0.4
V
ISINK = 200 μA
VOH
VLOGIC −
0.4
V
ISOURCE = 200 μA
Floating State Output Capacitance
9
pF
POWER REQUIREMENTS
VLOGIC
1.62
5.5
V
ILOGIC
1
µA
Power-on, −40°C to +105°C
1.3
µA
Power-on, −40°C to +125°C
0.5
µA
Power-down, −40°C to +105°C
1.3
µA
Power-down, −40°C to +125°C
VDD
2.7
5.5
V
Gain = 1
VREF + 1.5
5.5
V
Gain = 2
IDD
VINH = VDD, VINL = GND, VDD = 2.7 V to 5.5 V
Normal Mode8
2.3
2.53
mA
Internal reference off, −40°C to +85°C
3.4
3.8
mA
Internal reference on, −40°C to +85°C
2.3
2.6
mA
Internal reference off
3.4
4.2
mA
Internal reference on
All Power-Down Modes9
2
3.4
µA
Power-down to 1 kΩ, −40°C to +85°C
2
5
µA
Power-down to 1 kΩ, −40°C to +105°C
2
11
µA
Power-down to 1 kΩ, −40°C to +125°C
1
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2
VDD = 5 V. The device includes current limiting intended to protect the devices during temporary overload conditions. TJ can be exceeded during current limit.
Operation above the specified maximum operation junction temperature can impair device reliability.
3
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
4
Time to exit power-down to normal mode of operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.
5
Initial accuracy presolder reflow is ±750 µV. Output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
6
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
7
Voltage reference temperature coefficient is calculated as per the box method. See the Terminology section for further information.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All DACs powered down.



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