Data Sheet

AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 7 of 32

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications are TJ = −40°C to +125°C, typical

at TA = 25°C, unless otherwise noted.

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT VOLTAGE SETTLING TIME1

6

8

µs

¼ to ¾ scale settling to ±2 LSB

SLEW RATE

0.8

V/µs

DIGITAL-TO-ANALOG GLITCH IMPULSE1

1.4

nV-sec

1 LSB change around major carry (internal reference, gain = 1)

DIGITAL FEEDTHROUGH1

0.13

nV-sec

CROSSTALK1

Digital

0.1

nV-sec

Analog

−0.25

nV-sec

−1.3

nV-sec

Internal reference, gain = 2

DAC-to-DAC

−2.0

nV-sec

Internal reference, gain = 2

TOTAL HARMONIC DISTORTION2

−80

dB

At TA, bandwidth = 20 kHz, VDD = 5 V, output frequency (fOUT) = 1 kHz,

internal reference, gain = 2

OUTPUT NOISE SPECTRAL DENSITY1

300

nV/√Hz

DAC code = midscale, 10 kHz, gain = 2

OUTPUT NOISE1

6

µV p-p

0.1 Hz to 10 Hz, gain = 1

SIGNAL-TO-NOISE RATIO (SNR)

90

dB

At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz, internal

reference

SPURIOUS-FREE DYNAMIC RANGE

(SFDR)

83

dB

At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz, internal

reference

SIGNAL-TO-NOISE-AND-DISTORTION

RATIO (SINAD)

80

dB

At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz, internal

reference, gain = 2

1

See the Terminology section. Measured using internal reference and gain = 1, unless otherwise noted.

2

Digitally generated sine wave (fOUT) at 1 kHz.

TIMING CHARACTERISTICS

All input signals are specified with rise time (tR) = fall time (tF) = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL +

VINH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V. VREF = 2.5 V. All specifications are TJ = −40°C to +125°C, unless

otherwise noted.

Table 5.

1.62V ≤ VLOGIC < 2.7 V

2.7V ≤ VLOGIC ≤ 5.5 V

Parameter

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

t1

20

20

ns

SCLK High Time

t2

8

8

ns

SCLK Low Time

t3

10

12

ns

SYNC to SCLK Falling Edge Setup Time

t4

15

11

ns

Data Setup Time

t5

2

3

ns

Data Hold Time

t6

2

2

ns

SCLK Falling Edge to SYNC Rising Edge

t7

4

4

ns

Minimum SYNC High Time

t8

15

12

ns

SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates)

t9

870

830

ns

SYNC Falling Edge to SCLK Fall Ignore

t10

4

4

ns

LDAC Pulse Width Low

t11

12

12

ns

SYNC Rising Edge to LDAC Rising Edge

t12

27

27

ns

SYNC Rising Edge to LDAC Falling Edge

t13

25

25

ns

LDAC Falling Edge to SYNC Rising Edge

t14

840

840

ns

Minimum Pulse Width Low

t15

8

10

ns

Pulse Activation Time

t16

115

115

ns