Data Sheet

AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 11 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VOUT0

Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.

2

VDD

Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in parallel with a 0.1

µF capacitor to GND.

3

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data transfers in on

the falling edges of the next 24 clocks.

4

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data transfers at rates

of up to 50 MHz.

5

SDI

Serial Data Input. The AD5674/AD5674R/AD5679/AD5679R has a 24-bit input shift register. Data is clocked into the register on

the falling edge of the serial clock input.

6

GAIN

Span Set Pin. When this pin is tied to GND, all sixteen DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, all

sixteen DACs output a span of 0 V to 2 × VREF.

7

VOUT7

Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.

8

VOUT6

Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.

9

VOUT5

Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.

10

VOUT4

Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.

11

VOUT15

Analog Output Voltage from DAC 15. The output amplifier has rail-to-rail operation.

12

VOUT14

Analog Output Voltage from DAC 14. The output amplifier has rail-to-rail operation.

13

VOUT13

Analog Output Voltage from DAC 13. The output amplifier has rail-to-rail operation.

14

VOUT12

Analog Output Voltage from DAC 12. The output amplifier has rail-to-rail operation.

15, 16

GND

Ground Reference Point for All Circuitry on the Device.

17

LDAC

Load DAC. LDAC operates in two modes: asynchronously and synchronously. Pulsing this pin low updates any or all DAC

registers if the input registers have new data, which simultaneously updates all DAC outputs. This pin can also be tied

permanently low.

18

VLOGIC

Digital Power Supply. The voltage on this pin is specified in Table 2 and Table 3 in the Power Requirements section.

19

SDO

Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for readback. The serial

data transfers on the rising edge of SCLK and is valid on the falling edge.

20

RESET

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is

activated, the input register and the DAC register are updated with zero-scale or midscale, depending on the model in use.

21

VREF

Reference Output Voltage. When using the internal reference, this is the reference output pin. This pin is the reference output

by default.

22

VOUT11

Analog Output Voltage from DAC 11. The output amplifier has rail-to-rail operation.

23

VOUT10

Analog Output Voltage from DAC 10. The output amplifier has rail-to-rail operation.

24

VOUT9

Analog Output Voltage from DAC 9. The output amplifier has rail-to-rail operation.

25

VOUT8

Analog Output Voltage from DAC 8. The output amplifier has rail-to-rail operation.

26

VOUT3

Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.

27

VOUT2

Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.

28

VOUT1

Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.

EPAD

Exposed Pad. The exposed pad must be tied to GND.

1

VOUT0

2

VDD

3

SYNC

4

SCLK

5

SDI

6

GAIN

7

VOUT7

17 LDAC

18 VLOGIC

19 SDO

20 RESET

21 VREF

16 GND

15 GND

TOP VIEW

(Not to Scale)

AD5679R/AD5679/AD5674R/AD5674

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE

TIED TO GND.