AD5674/AD5674R/AD5679/AD5679R

Data Sheet

Rev. B | Page 8 of 32

Figure 2. Serial Write Operation

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH)/2. See Figure 4 and

Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V. VREF = 2.5 V. All specifications are TJ = −40°C to +125°C, unless otherwise noted.

VDD = 2.7 V to 5.5 V.

Table 6.

1.62V ≤ VLOGIC < 2.7 V

2.7V ≤ VLOGIC ≤ 5.5 V

Parameter

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

t1

130

110

ns

SCLK High Time

t2

33

23

ns

SCLK Low Time

t3

12

7

ns

SYNC to SCLK Falling Edge

t4

80

80

ns

Data Setup Time

t5

2

2

ns

Data Hold Time

t6

2

2

ns

SCLK Falling Edge to SYNC Rising Edge

t7

35

10

ns

Minimum SYNC High Time

t8

55

32

ns

SDO Data Valid from SCLK Rising Edge

t9

130

75

ns

SYNC Rising Edge to SCLK Falling Edge

t10

15

8

ns

SYNC Rising Edge to SDO Disable

t11

218

210

ns

t4

t3

SCLK

SYNC

SDI

t1

t2

t5

t6

t7

t14

t9

t8

DB23

t10

t11

t12

LDAC1

LDAC2

t13

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

RESET

t15

t16

VOUT

DB0