RT8800AGQV datasheet(10/21 Pages) RICHTEK

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RT8800A

DS8800A-04 August 2007

www.richtek.com

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Applications Information

The RT8800A is a general-purposed multi-phase

synchronous buck controller dedicating for high power

density applications. The RT8800A operates with 2 or 3

synchronous buck switching stages in interleaved phase

set automatically. The multiphase architecture provides

high output current while maintaining low power dissipation

on power devices and low stress on input and output

capacitors.

Initialization

The RT8800A initiates after 2 pins are ready : VDD pin

power on reset (POR) and DVD pin is higher than 1V. VDD

POR is to make sure RT8800A is powered by a voltage

high enough for normal work. The rising threshold voltage

of VDD POR is 4.2V typically. At VDD POR, RT8800A

checks PWM3 status to determine phase number of

operation. Pull high PWM3 for two-phase operation. The

unused current sense pins should be connected to GND

or left floating.

DVD is to make sure that ATX12V is ready for the

companion MOSFET drivers to work normally. Connect a

voltage divider from ATX12V to DVD pin as shown in the

Typical Application Circuit. Make sure that DVD pin voltage

is below its threshold voltage before drivers are ready and

above its threshold voltage for minimum ATX12V during

normal operation. If one of VDD and DVD is not ready,

RT8800A keeps its PWM outputs high impedance and

the companion drivers turn off both upper and lower

MOSFETs.

Soft-Start

After VDD and DVD are ready, RT8800A initiates its soft

start cycle as shown in Figure 1. The error amplifier and

PWM comparator are triple-input devices. The non-inverting

input whichever is smaller dominates the behavior of the

device. The soft start function generates SS and SSE for

the non-inverting input of PWM comparator and error

amplifier respectively where SSE = SS - VGS. VGS is

threshold voltage of internal MOSFET. The typical soft-

start duration is 3ms. The soft start can be sliced to

several time frames with specific operation respectively.

1) Mode 1 (SS < VRAMP_Valley)

Initially the COMP stays in the positive saturation due to

offset of the error amplifier. Since SS < VRAMP_Valley, the

PWM comparator keeps its output low and VOUT is zero.

2) Mode 2 (VRAMP_Valley < SS < Cross-over)

Since VRAMP_Valley < SS < Cross-over, SS dominates the

non-inverting inputs of the PWM comparators. The PWM

duty cycles increase according to the ramping up SS

signal. The output voltage ramps up accordingly. However

as VOUT increases, the difference between VOUT and SSE

(SS - VGS) is reduced and COMP leaves the saturation

and declines. The takeover of SS lasts until it meets the

COMP. During this interval, since the feedback path is

broken, the converter is operated in the open loop.

3) Mode3 (Cross-over < SS < VGS + VPI)

When the VCOMP takes over the non-inverting input for PWM

Amplifier and when SSE (SS - VGS) < VPI, the output of

the converter follows the ramp input, SSE (SS - VGS).

Before the crossover, the output follows SS signal. And

when VCOMP takes over SS, the output is expected to

follow SSE (SS - VGS). Therefore the deviation of VGS is

represented as the falling of VOUT for a short while. The

COMP is observed to keep its decline when it passes the

cross-over, which shortens the duty width and hence the

falling of VOUT happens. Since there is a feedback loop for

the error amplifier, the output's response to the ramp input,

SSE (SS - VGS) is lower than that in Mode 2.

4) Mode 4 (SS > VGS + VPI)

When SS > VGS + VPI, the output of the converter follows

the desired VPI signal and the soft start completes.

However, the SS keeps ramping up to 3.3V and stays

there. The PGOOD pin trips to high impedance as SS

reaches 3.3V.

Soft Start

SSE

PWM

Figure 1. Soft Start Block Diagram.

RT8800AGQV Datasheet(PDF) 10 Page - Richtek Technology Corporation

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