RT8800AGQV datasheet(14/21 Pages) RICHTEK

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RT8800A

DS8800A-04 August 2007

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Rewriting Equation (3), we get

CSN

LX_Valley

COMM

≥

The technique mentioned above also provides output voltage

offset function specified by Intel ® VRD10.x. The offset

voltage level is calculated as:

CSN

ADJ

OFFSET

Enough bias current is required for a Schottky to act like

a voltage source. Users should choose the appropriate

RCS based on the IV characteristic of the diode

(Figure 12)

Figure 12

Zone 1

Zone 2

IV Characteristic

According to Figure 12, the forward voltage of diode will

be different results from the different conduction current.

So when the characteristic of diode in the circuit you

design is in zone 1, this will result in Spec. mis-met. It is

because when the VCORE is changed during DVID, the

node VCORE- VF is also changed to produce the differential

conduction current of diode

ΔI and the ΔI will result in

producing the differential forward voltage of diode

ΔVF

Referring to Equation (1). The

ΔVF would get ΔIX. Then

the VCORE must be subtracted the extra voltage V(EXT)(

ΔIX

x RADJ ) during DVID. So you will get the

ΔVCORE = V(MAX)

- V(MIN) - V(EXT) during DVID tests. In order to reduce the

effect results from diode. The better choice is to decrease

the Rcs to increase the conduction current of diode I to

get better V characteristic of diode in Zone 2.

Over Voltage Protection (OVP)

The RT8800A continuously monitors voltage at FB pin.

OVP is triggered if FB voltage is 500mV higher than the

voltage at PI pin. RT8800A latches off and turns on lower

MOSFET to protect the load from damage upon on OVP

trip. It can only be reset by DVD and VDD pins.

Current Ratio Setting

Current ratio adjustment is possible as described below.

It is important for achieving thermal balance in practical

application where thermal conditions between phases are

not identical. Figure 13 shows the application circuit of

GM for current ratio requirement. According to Basic Circuit

Theory, if

then

)

//R

With other phase kept unchanged, this phase would share

(RPX+RSX)/RPX times current than other phases. Figure 14

and 15 show different current ratio setting for the power

stage when Phase 3 is programmed 2 times current than

other phases. Figure 16 and 17 compare the above current

ratio setting results.

Figure 13

(4)

RLX

ILX

VOUT

RSX

+ VX -

RPX

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