R31DS0022EU0110 Rev.1.1

Page 33

Feb 6, 2023

8V97052 Datasheet

5.8

Register 7

Table 65. Register 7 Bit Allocation[1][2]

Table 66. Register 7: 1-bit Loss of Digital Lock. Function Description

Table 67. Register 7: 1-bit Loss of Analog Lock. Function Description

Table 68. Register 7: 1-bit SPI Error. Function Description

Name

Description

Function[1]

1. This bit is a sticky bit and needs to be cleared with a SPI write of 1 to detect further Loss of Digital Lock occurrences.

Loss_Dig_Lock

LOSS_DIG_LOCK

0 = Locked since last time register was cleared

1 = Loss of Digital Lock since last time register was

cleared

Name

Description

Function[1]

1. This bit is a sticky bit and needs to be cleared with a SPI write of 1 to detect further Band Selection occurrences.

Loss_Anlg_Lock

LOSS_ANLG_LOCK

0 = Band Selection remained the same since last

time register was cleared

1 = Band selection occurred since last time

register was cleared

Name

Description

Function[1]

1. Spi_error Bit goes high if the SPI interface detects a cycle with the incorrect number of SCLK cycles between nCS asserted Low and

nCS asserted High. The SPI interface expects 32 clock cycles between nCS asserted Low and nCS asserted High. Any Read/Write via

the SPI interface with more or less than 32 clock cycles will result in the Spi_error Bit switched to 1. This bit is a sticky and needs to be

cleared with a SPI write of 1 in order to detect further possible SPI Write/Read errors.

Spi_error

SPI_ERROR

0 = No SPI write error detection

1 = SPI Write error

NOTE 2. RO bits are Read Only bits.

DEV_ID (RO)

NOTE 1. SB bits are Sticky bits and need to be cleared.

RF DIVIDER

RESERVED

REV_ID

CONTROL

BITS