8V97052 datasheet(10/47 Pages) RENESAS

10 / 47 page

R31DS0022EU0110 Rev.1.1

Page 10

Feb 6, 2023

8V97052 Datasheet

Figure 3. Simplified PFD Circuit using D-type Flip-flop

The band select logic operates between 125kHz and 500kHz. The band select clock divider needs to be set to

divide down the PFD frequency to between 125kHz to 500kHz (logic maximum frequency).

2.6

PFD Frequency

The VCO band selection can be used while operating at PFD frequencies up to 310MHz.

If the application requires the PFD frequency to be higher than 100MHz in integer mode, the user can use one of

the following two techniques (Technique A is the recommended procedure):

1. The user can use the extended register ExtBndSelDiv[4:1] bits (Bits [D6:D3]) in Register 6. These additional

band select divider bits extend the band select divider from 8-bits (available in Register 4) to 12-bits. The four

additional band select divider bits in

divided by the band select divide value must be 500kHz and 125kHz.

▪ If choosing this second technique, the user must follow the three following steps:

2. Disable the phase adjust function by setting the bit D28 in Register 1 to 0, keep the PFD frequency lower than

125MHz, and program the desired VCO frequency.

3. Enable the phase adjust function by setting BAND_SEL_DISABLE (Bit D28 in Register 1) to 1.

4. Set the desired PFD frequency and program the relevant R divider and N counter values.

In either technique, the lock detect precision should be programmed to be lower than the PFD period using the bit

[D7] in Register 2 and the bits [D27:D26] in Register 6 (refer to Table 4).

2.7

External Loop Filter

The 8V97052 requires an external loop filter. The design of that filter is application specific. For additional

information, refer to Applications Information.

2.8

Phase Detector Polarity

The phase detector polarity is set by bit D6 in Register 2. This bit should be set to 1 when using a passive loop

filter or a non-inverting active loop filter. If an inverting active filter is used, this bit should be set to 0.

VDD

REF_IN x (1+D)/R

CP_OUT

VDD

DELAY

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