8V97052 datasheet(5/47 Pages) RENESAS

5 / 47 page

R31DS0022EU0110 Rev.1.1

Page 5

Feb 6, 2023

8V97052 Datasheet

1. Pin Information

1.1

Pin Assignments

1.2

Pin Descriptions

Table 1. Pin Descriptions[1]

Name

Type

Description

SCLK

LVCMOS input

Pull-down

Serial clock input. High-Impedance CMOS input. 1.8V logic. 3.3V

tolerant.

SDI

LVCMOS input

Pull-up

Serial data input. High-Impedance CMOS input. 1.8V logic. 3.3V

tolerant.

nCS

LVCMOS input

Pull-down

Load enable. High-Impedance CMOS input. 1.8V logic. 3.3V

tolerant. Active low.

LVCMOS input

Pull-up

Chip enable. On logic low, powers down the device and puts the

charge pump into High-Impedance mode. Powers up the device on

logic High.

FLSW

Analog

Fast lock switch. A connection should be made from the loop filter

to this pin when using the fast lock mode.

V_CP

Power

Charge pump power supply. V_CP must have the same value as

VDDA. Place decoupling capacitors to the ground plane as close to

this pin as possible.

CP_OUT

Analog

Charge pump output. When enabled, this output provides ±ICP to

the external loop filter. The output of the loop filter is connected to

VTUNE to drive the internal VCO.

GND_CP

Ground

Charge pump power supply ground.

GNDA

Ground

VCO analog power supply ground.

VDDA

Power

Analog supply. This pin ranges from 3.3V ±5%. VDDA must have

the same value as VDDD.

8V97052 Datasheet(PDF) 5 Page - Renesas Technology Corp

8V97052 Datasheet(HTML) 5 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Descarga

Enlace URL