S25FL128SDPNFAQ datasheet(55/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

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S25FL128S/S25FL256S

7.5.5

Bank Address Register

Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h) and Bank

The Bank Address register supplies additional high order bits of the main flash array byte boundary address for legacy commands

that supply only the low order 24 bits of address. The Bank Address is used as the high bits of address (above A23) for all 3-byte

address commands when EXTADD=0. The Bank Address is not used when EXTADD = 1 and traditional 3-byte address commands

are instead required to provide all four bytes of address.

Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By default (power up

reset, hardware reset, and software reset), it is cleared to 0 for 3 bytes (24 bits) of address. When set to 1, the legacy commands will

require 4 bytes (32 bits) for the address field. This is a volatile bit.

7.5.6

ECC Status Register (ECCSR)

Related Commands: ECC Read (ECCRD 18h). ECCSR does not have user programmable non-volatile bits. All defined bits are

volatile read only status. The default state of these bits are set by hardware. See Section 9.5.1.1 Automatic ECC on page 100.

The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read command is

written followed by an ECC unit address. The contents of the status register then indicates, for the selected ECC unit, whether there

is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes of data, or that ECC is disabled for that ECC unit.

ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC unit data.

ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures and ECC is enabled.

ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to another. These

bits should be treated as “don’t care” and ignored by any software reading status.

Table 32. Bank Address Register (BAR)

Bits

Field Name

Function

Type

Default State

Description

EXTADD

Extended Address

Enable

Volatile

1 = 4-byte (32-bits) addressing required from command.

0 = 3-byte (24-bits) addressing from command + Bank

Address

6 to 1

RFU

Reserved

Volatile

00000b

Reserved for Future Use

BA24

Bank Address

Volatile

A24 for 256-Mbit device, RFU for lower density device

Table 33. ECC Status Register (ECCSR)

Bits

Field Name

Function

Type

Default

State

Description

7 to 3

RFU

Reserved

Reserved for Future Use

EECC

Error in ECC

Volatile, Read only

1 = Single Bit Error found in the ECC unit eight

bit error correction code

0 = No error.

EECCD

Error in ECC unit

data

Volatile, Read only

1 = Single Bit Error corrected in ECC unit

data.

0 = No error.

ECCDI

ECC Disabled

Volatile, Read only

1 = ECC is disabled in the selected ECC unit.

0 = ECC is enabled in the selected ECC unit.

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