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S25FL128SDPNFAQ Datasheet(PDF) 84 Page - Cypress Semiconductor |
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S25FL128SDPNFAQ Datasheet(HTML) 84 Page - Cypress Semiconductor |
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84 / 149 page  Document Number: 001-98283 Rev. *M Page 83 of 148 S25FL128S/S25FL256S 9.3.16 Write VDLR (WVDLR 4Ah) Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation. The WVDLR command is entered by shifting the instruction and the data byte on SI. CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WVDLR command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz. Figure 60. Write VDLR (WVDLR) Command Sequence 9.3.17 Data Learning Pattern Read (DLPRD 41h) The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is 133 MHz. Figure 9.5 DLP Read (DLPRD) Command Sequence IInstruction Data Learning Pattern 1 3 2 10 9 8 7 6 5 4 0 14 13 12 15 0 1 7 6 5 3 2 SCK SI SO MSB High Impedance CS 0 1 7 6 5 4 3 2 MSB 4 11 # IInstruction Data Learning Pattern 1 3 2 10 9 8 7 6 5 4 0 14 13 12 15 0 1 7 6 5 3 2 SCK SI SO MSB High Impedance CS 0 1 7 6 5 4 3 2 MSB 4 11 Data Learning Pattern 18 17 16 22 21 20 23 0 1 7 6 5 3 2 MSB 4 19 # |
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