CLK1

DA[15:0]

DB[15:0]

ts(DATA)

th(DATA)

A0

A1

A2

AN

AN+1

A3

B0

B1

B2

BN

BN+1

B3

T0039-01

CLK2

DA[15:0]

DB[15:0]

ts(DATA)

th(DATA)

A0

A1

A2

AN

AN+1

A3

B0

B1

B2

BN

BN+1

B3

PLLLOCK

td(PLLLOCK)

T0040-01

Interleave Bus Mode

IOUTB1

IOUTB2

IOUTA1

IOUTA2

16-Bit

DAC

2fDATA

2y–16y fDATA

fDATA

y2

16-Bit

DAC

2fDATA

y2

FIR1

Edge Triggered

Input Latches

• ••

• ••

DA[15:0]

DEMUX

B0025-02

DAC5686

www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

Figure 32. Dual-Bus Mode Timing Diagram (PLL Mode)

Figure 33. Dual-Bus Mode Timing Diagram (External Clock Mode)

In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data

bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 34 shows

the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 35.

Figure 34. Interleave Bus Mode Data Path

Copyright © 2003–2009, Texas Instruments Incorporated

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