Analog Current Outputs

IOUT1

IOUT2

S(1)

S(1)C

RLOAD

RLOAD

S(2)

S(2)C

S(N)

S(N)C

AVDD

S0032-01

DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

Figure 50 shows a simplified schematic of the current source array with corresponding switches. Differential

switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or

its complementary negative output node IOUT2. The output impedance is determined by the stack of the current

sources and differential switches and is typically >300 k

Ω in parallel with an output capacitance of 5 pF.

The external output resistors are terminated to AVDD. The maximum output compliance at nodes IOUT1 and

IOUT2 is limited to AVDD + 0.5 V, determined by the CMOS process. Beyond this value, transistor breakdown

can occur, resulting in reduced reliability of the DAC5686 device. The minimum output compliance voltage at

nodes IOUT1 and IOUT2 equals AVDD – 0.5 V. Exceeding the minimum output compliance voltage adversely

affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended

or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed

0.5 V.

Figure 50. Equivalent Analog Current Output

The DAC5686 can be easily configured to drive a doubly terminated 50-

Ω cable using a properly selected RF

transformer. Figure 51 and Figure 52 show the 50-

Ω doubly terminated transformer configuration with 1:1 and

4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer must be

connected to AVDD to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a

0.5-Vpp output for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer.

46

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