I

fullscale

+

16 V

extio

R

biasj

(GAINCODE ) 1)

16

B 1 *

FINEGAIN

3072

I

fullscale

+

16 V

extio

R

biasj

(GAINCODE ) 1)

16

B 1 *

FINEGAIN

3072

DIGITAL INPUTS

DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

sleepa: When asserted, DACA is put into the sleep mode.

daca_gain[11:8]: Coarse gain control for DACA; the full-scale output current is:

where GAINCODE is the decimal equivalent of daca_gain [11:8] {0…15} and the FINEGAIN is daca_gain [7:0] as

2s complement {–127…128}.

Register Name: dacb_offset_lsb (2s complement)

MSB

LSB

dacb_offset[7:0]

0

0

0

0

0

0

0

0

dacb_offset[7:0]: The lower 8 bits of the DACB offset

Register Name: dacb_gain_lsb (2s complement)

MSB

LSB

dacb_gain[7:0]

0

0

0

0

0

0

0

0

dacb_gain[7:0]: The lower 8 bits of the DACB gain control register. These lower 8 bits are for fine gain control.

This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%

range.

Register Name: dacb_offset_gain_msb (2s complement)

MSB

LSB

dacb_offset[10:8]

sleepb

dacb_gain[11:8]

0

0

0

0

0

0

0

0

dacb_offset[10:8]: The upper 3 bits of the DACA _offset

sleepb: When asserted, DACB is put into the sleep mode.

dacb_gain[11:8]: Coarse gain control for DACB; the full-scale output current is:

where GAINCODE is the decimal equivalent of dacb_gain [11:8] {0…15} and the FINEGAIN is dacb_gain [1:0] as

2s complement {–127…128}.

Figure 45 shows a schematic of the equivalent CMOS digital inputs of the DAC5686. DA[15:0], DB[15:0], SLEEP,

PHSTR, TxENABLE, QFLAG, SDIO, SCLK, and SDENB have pulldown resistors and RESETB has a pullup

resistor internal to the DAC5686. The pullup and pulldown circuitry is approximately equivalent to 100 k

Ω. See

the specification table for logic thresholds.

42

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