DA[15:0]

DB[15:0]

SLEEP

PHSTR

TXENABLE

QFLAG

SDIO

SCLK

SDENB

Internal

Digital In

IOVDD

IOGND

RESETB

Internal

Digital In

IOVDD

IOGND

S0027–02

400 W

400 W

100

kW

100

kW

CLOCK INPUT AND TIMING

CLK

Internal

Digital In

CLKC

CLKGND

R1

10 k

Ω

CLKVDD

R1

10 k

Ω

R2

10 k

Ω

R2

10 k

Ω

CLKVDD

CLKVDD

S0028-01

DAC5686

www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

Figure 45. CMOS/TTL Digital Equivalent Input

Figure 46 shows an equivalent circuit for the clock input.

Figure 46. Clock Input Equivalent Circuit

Figure 47, Figure 48, and Figure 49 show various input configurations for driving the differential clock input

(CLK/CLKC).

Copyright © 2003–2009, Texas Instruments Incorporated

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