1.

General description

The 74LVC161 is a synchronous presettable binary counter which features an internal

look-ahead carry and can be used for high-speed counting. Synchronous operation is

provided by having all flip-flops clocked simultaneously on the positive-going edge of the

clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level

or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting

action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter

on the positive-going edge of the clock (provided that the set-up and hold time

requirements for PE are met). Preset takes place regardless of the levels at count enable

inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four

outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins

CP, PE, CET and CEP (thus providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs

(pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the

terminal count output (pin TC). The TC output thus enabled will produce a HIGH output

pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be

used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by tPHL

(propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula:

It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to

most advanced CMOS compatible TTL families.

2.

Features and benefits

 5 V tolerant inputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 Asynchronous reset

 Synchronous counting and loading

 Two count enable inputs for n-bit cascading

 Positive edge-triggered clock

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous

reset

Rev. 6 — 30 September 2013

Product data sheet

f

max

1

t

PHL max



t

su

+

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=