74LVC161

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Product data sheet

Rev. 6 — 30 September 2013

12 of 22

NXP Semiconductors

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous reset

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 9.

Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and maximum frequency

mna911

CP input

Qn, TC output

tPHL

tPLH

tW

1/fmax

VM

VOH

VI

GND

VOL

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 10. Input (CET) to output (TC) propagation delays

mna912

tPHL

tPLH

VM

VM

TC output

CET input

GND

VI

VOH

VOL

Fig 11. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays, and the master

reset to clock (CP) removal times

mna913

MR input

CP input

Qn, TC output

tPHL

tW

trec

VM

VOH

VI

VI

GND

GND

VOL

VM

VM