NRF52820-QDAA-R datasheet(39/437 Pages) NORDIC

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Core components

The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in

the code example below using a READER EasyDMA channel as an example:

#define BUFFER_SIZE 4

typedef struct ArrayList

{

uint8_t buffer[BUFFER_SIZE];

} ArrayList_type;

ArrayList_type ReaderList[3] __at__ 0x20000000;

MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;

MYPERIPHERAL->READER.PTR = &ReaderList;

MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;

The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA

uses the READER.MAXCNT register to determine when the buffer is full.

buffer[0]

buffer[1]

0x20000000 : ReaderList[0]

0x20000004 : ReaderList[1]

0x20000008 : ReaderList[2]

buffer[2]

buffer[3]

READER.PTR = &ReaderList

buffer[0]

buffer[1]

buffer[2]

buffer[3]

buffer[0]

buffer[1]

buffer[2]

buffer[3]

Figure 6: EasyDMA array list

4.7 AHB multilayer

AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is

resolved using priorities.

Each bus master is connected to all the slave devices using an interconnection matrix. The bus masters are

assigned priorities, which are used to resolve access when two (or more) bus masters request access to

the same slave device. When that occurs, the following rules apply:

• If two (or more) bus masters request access to the same slave device, the master with the highest

priority is granted the access first.

• Bus masters with lower priority are stalled until the higher priority master has completed its

transaction.

• If the higher priority master pauses at any point during its transaction, the lower priority master in

queue is temporarily granted access to the slave device until the higher priority master resumes its

activity.

• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.

Some peripherals, such as RADIO, do not have a safe stalling mechanism (no internal data buffering, or

opportunity to pause incoming data). Being a low priority bus master might cause loss of data for such

peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, follow

these guidelines:

4463_156 v1.0

NRF52820-QDAA-R Datasheet(PDF) 39 Page - Nordic Semiconductor

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