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NRF52820-QDAA-R Datasheet(PDF) 67 Page - Nordic Semiconductor |
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NRF52820-QDAA-R Datasheet(HTML) 67 Page - Nordic Semiconductor |
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67 / 437 page ![]() Power and clock management When read, this register will return the value of the POWER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description A-B W S[i]POWER (i=0..1) Keep RAM section Si of RAMn on or off in System ON mode On 1 On C-D W S[i]RETENTION (i=0..1) Keep retention on RAM section Si when RAM section is switched off On 1 On 5.3.7.22 RAM[n].POWERCLR (n=0..3) Address offset: 0x908 + (n × 0x10) RAMn power control clear register When read, this register will return the value of the POWER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description A-B W S[i]POWER (i=0..1) Keep RAM section Si of RAMn on or off in System ON mode Off 1 Off C-D W S[i]RETENTION (i=0..1) Keep retention on RAM section Si when RAM section is switched off Off 1 Off 5.3.8 Electrical specification 5.3.8.1 Regulator operating conditions Symbol Description Min. Typ. Max. Units VDD,POR VDD supply voltage needed during power-on reset 1.75 V VDD Normal voltage mode operating voltage 1.7 3.0 3.6 V VDDH High voltage mode operating voltage 2.5 3.7 5.5 V CVDD Effective decoupling capacitance on the VDD pin 2.7 4.7 5.5 µF CDEC4 Effective decoupling capacitance on the DEC4 pin 0.7 1 1.3 µF 5.3.8.2 Regulator specifications, REG0 stage Symbol Description Min. Typ. Max. Units VREG0OUT REG0 output voltage 1.8 3.3 V VREG0OUT,ERR REG0 output voltage error (deviation from setting in REGOUT0 on page 36) -10 5 % VREG0OUT,ERR,EXT REG0 output voltage error (deviation from setting in REGOUT0 on page 36), extended temperature range -10 7 % VVDDH-VDD Required difference between input voltage (VDDH) and output voltage (VDD, configured in REGOUT0 on page 36), VDDH > VDD 0.3 V 4463_156 v1.0 67 |
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