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NRF52820-QDAA-R Datasheet(PDF) 24 Page - Nordic Semiconductor |
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NRF52820-QDAA-R Datasheet(HTML) 24 Page - Nordic Semiconductor |
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24 / 437 page ![]() Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A W ERASEPAGEPARTIAL Register for starting partial erase of a page in code area The value is the address to the page to be partially erased (address of the first word in page). The erase must be enabled using CONFIG.WEN before every erase page partial and disabled using CONFIG.WEN after every erase page partial. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased. 4.3.9.10 ERASEPAGEPARTIALCFG Address offset: 0x51C Register for partial erase configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x0000000A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 ID Access Field Value ID Value Description A RW DURATION Duration of the partial erase in milliseconds The user must ensure that the total erase time is long enough for a complete erase of the flash page. 4.3.10 Electrical specification 4.3.10.1 Flash programming Symbol Description Min. Typ. Max. Units nWRITE Number of times a 32-bit word can be written before erase 2 nENDURANCE Erase cycles per page 10000 tWRITE Time to write one 32-bit word 42.51 µs tERASEPAGE Time to erase one page 87.51 ms tERASEALL Time to erase all flash 1731 ms tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total execution time for one partial page erase is defined as ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc. 1.091 4.4 FICR — Factory information configuration registers Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration. 1 Applies when HFXO is used. Timing varies according to HFINT accuracy when HFINT is used. 4463_156 v1.0 24 |
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