STLC5460 datasheet(10/54 Pages) STMICROELECTRONICS

10 / 54 page

The microprocessor interface type is set via P0

pin as shown hereafter :

P1 is an outputand it is not used if P0 = 1.

The device selects automatically either Motorola

interface or Intel Interface.

Automatical selection

Intel MUX mode

Motorola MUX mode

Intel DEMUX mode

Motorola DEMUX mode

If A0 = 1

P1 pin delivers WAIT automatically

If A0 = 0

P1 pin delivers READY automatically

Moreover, for a multiplexed mode

µP interface,

A1 to A3 pins mean :

A1 = 1: CS signal provided by the system is not

inverted by the device

A1 = 0: CS signal provided by the system is in-

verted by the device

A2 = 1: AS signal provided by the system is not

inverted by the device

A2 = 0: AS signal provided by the system is in-

verted by the device

A3 = 1: DS signal provided by the system is not

inverted by the device

A3 = 0: DS signal provided by the system is in-

verted by the device.

C/I AND MON CHANNELS, EXTRA CHANNELS

The Command/indicate and Monitor channels can

be validated or not:

if validated, the C/I and MON protocol controllers

operate and it is not possible to use this channels

for switching, if not validated the protocols are in-

hibited and the channels can be used as ex-

trachannels for switching.

Command/Indicate Protocol

Sixteen C/I channels are implemented, one bit of

the configuration register MCONF1, indicates the

number of bits of the primitive (four or six bits) for

all the channels.

To transmit a primitive into one of the 16 chan-

nels, the mp loads the primitive (4 or 6 bits) into

source register and the number of the C/I chan-

nel into destination register with W/R bit of com-

mand register at ”0”.

The two more significant bits of the source regis-

ter indicates if the primitive, bit0/5 of the same

once, twice or more .

When a new primitive has been received twice

identical, on one of the 16 C/I channels, an inter-

rupt is generated, the number of the C/I channel

(4 bits) is written in the Receive C/I status regis-

ter , and the primitive received is in the Auxiliary

Memory, all accessible to the

µp

Moreover, the microprocessor can read directly

the 16 primitives that have been received and

stored into the Receive C/I Memory. To read this

memory the

µp load in the Source Register the

number of Receive C/I channel it wants, and in

the destination register reads the primitive (4 or 6

bits) with a seventh bit which indicates whether

the primitive has been received once or twice

identical. vedi figura read aux mem Receive C/I

channels.

Monitor Channel Protocol

Sixteen Monitor channels are implemented. To

transmit a message the

µp load into destination

the number of MON channels, and into source

BYTE Bit of Command Register is at 1.

This procedure is repeated for each byte of the

message if it is longer than one byte.

When a new byte has been received twice identi-

cal from one of the sixteen Monitor channels

an interrupt is generated, the number of MON

channel (4 bits) is written in Receive Monitor

Status Register and the last byte received is writ-

ten in Receive data Monitor Channel Memory.

The remote transmitter will transmit the next byte

after reading of this register by the local micro-

processor.

INSERTION - EXTRACTION

This function allows to insert data into GCI and

PCM channels and to extract data from GCI and

PCM interface. These data are provided either by

the microprocessor or by an internal Pseudo Ran-

dom Sequence Generator.

Insertion

Two programmable registers (Insert A and B)

contain the data to insert into two output time

slots continuously. To perform an insertion, four

registers are programmed by the microprocessor:

- in the Insert A and/or B Registers it writes the

data to insert.

- in the Source registers it writes the A and/or B

- in the Destination Register it writes the output

interface, PCM or GCI, and the Time Slot se-

lected.

STLC5460

10/54

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