STLC5460 datasheet(28/54 Pages) STMICROELECTRONICS

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EXTRACTION A REGISTER (EXT A)

EA7

EA6

EA5

EA4

EA3

EA2

EA1

EA0

After Reset 00 (H)

EA 0/7

This register contains the data extracted during the Time Slot of Input multiplex

indicated by the Command Memory. After loading, EXT interrupt is generated, in

accordance with NEWE bit of Comparison Register

EXTRACTION B REGISTER (EXT B)

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

After Reset 00 (H)

EB 0/7

This register contains the data extracted during the Time Slot of Input multiplex

indicated by the Command Memory. After loading, EXT interrupt is generated in

accordance with NEWE bit of Comparison Register.

INTERRUPT REGISTER (INT)

LSYNC

PDIF

PRS

MONR

MONT

CIR

EXT

INS

After Reset 00 (H)

LSYNC

Lost synchronisation.

LSYNC = 0, PFS signal frequency is correct.

LSYN = 1. PFS signal has not occurred when expected,

or if Double clock the number of clock pulses received is odd,

or the data rate of one PCM received is not Modulo 4 bits at 8 Mb/s,

or the data rate of one PCM received is not Modulo 2 bits at 4 Mb/s.

PDIF

PCM different.

PDIF = 1. If one (or more) comparison (validated by the Comparison Register)

between PCM is different.

PRS

Pseudo Random Sequence .

When the PRS analyser is validated (SAV =1), PRS bit is put to ”one” if the

synchronisation is performed or lost (see PRSR bit of Status Register).

MONR

Monitor Channel Receive.

When this bit is at ”1”, a byte has been received from the Monitor Channel defined by

Receive Monitor Status Register (or an event)

MONT

Monitor Channel Transmit.

When this bit is at ”1”, the Monitor Channel (defined by Transmit Monitor Status

CIR

Command Indicate Receive.

When this bit is at ”1”, a new primitive has been received from the Command/Indicate

channel defined by the Receive Command/Indicate Status Register

EXT

Extract

When this bit goes to ”1”, the Extract Register A or/and B can be read during 120

microseconds before changing.

INS

Insert

When this bit goes to ”1”, the content of Insert Register A or/and B has been

transmitted. During 120 microseconds before the next transmission, the

microprocessor can write a new word in accordance with TIM (Bit of CR Register).

STLC5460

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