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STLC5460 Datasheet(PDF) 36 Page - STMicroelectronics |
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STLC5460 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 54 page ![]() DEL, ISPP and PFSP bits of PCM Configuration Register are at zero (no delay)) 7 61 0 5 4 3 Bit3 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Time Slot 31 Time Slot 0 PFS TXD0/3 TDM0/3 FSC delivered by the circuit t1 t5h t5l t3 t4 PDC TS0/3 t2 RXD0/3 t6 t7 t8 CLOCK TIMING Synchronization signals delivered by the system Clocks received by the LCIC tx Parameter T min. T typ. T max. Unit t1=1/f1 Clock Period if f1 = 16384KHz Clock Period if f1 = 8192KHz Clock Period if f1 = 4096KHz 60 120 239 61 122 244 62 124 249 ns ns ns t2 Bit-time if f1 = 16384KHz Bit-time if f1 = 8192KHz Bit-time if f1 = 4096KHz 122 244 488 ns ns ns t3 Set up time PFS/PDC 20 t1-20 ns t4 Hold time PFS/PDC 20 12500-t1 ns t5 Clock ratio t5h/t5l 75 100 125 % t6 PDC to data 50pF PDC to data 100pF 50 100 ns ns t7 Set up time data/DCL 20 ns t8 Hold time data/DCL 20 ns STLC5460 36/54 |
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