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STLC5464 Datasheet(PDF) 39 Page - STMicroelectronics |
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STLC5464 Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 83 page  V - CLOCK TIMING (continued) V.2 - TDM Synchronization t1 t3 Bit 0, Time Slot 0 t7 t7 DCLK de live re d by the Multi-HDLC FS CG d e livere d by the Multi-HDLC DOUT0/7, CB DIN0/8 The four Multiplex Configura tion Re giste rs a re a t z e ro (no d e lay be twe e n FS a nd Multiplexe s). t8 CLOCK A (o r B) t4 t2 t5 Bit 7, Time S lot 31 ECHO t9 t6 Figure 28 : Synchronization Signals received by the Multi-HDLC Symbol Parameter Min. Typ. Max. Unit t1 Clock Period if 4096kHz Clock Period if 2048kHz Id CLOCKA or B 244 488 Id CLOCKA or B ns ns t2 Delay between CLOCK A or B and DCLK (30pF) 5 30 ns t3 Set-up Time FS/DCLK 20 t1-20 ns t4 Hold Time FS/DCLK 20 ns t5 Duration FS 244 125000-244 ns t6 DCLK to Data 50pF DCLK to Data 100pF 50 100 ns t7 Set-up Time Data/DCLK 20 ns t7 Hold Time Data/DCLK 20 ns t8 Set-up Echo/DCLK (rising edge) 155 ns t9 Hold Time Echo/DCLK (rising edge) 205 ns STLC5464 39/83 |
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