STLC5464 datasheet(6/83 Pages) STMICROELECTRONICS

6 / 83 page

LIST OF FIGURES

Page

PIN INFORMATION . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..

BLOCK DIAGRAM . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..

Figure 1

: General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .... ..... ..... . .

III

FUNCTIONAL DESCRIPTION . . . . ...... ... ..... . . ... .. . . . . ..... ..... ....

Figure 2

: Switching Matrix Data Path . . . . . . . .... . . ... . . ... . . .... ..... ....

Figure 3

: Unidirectional and Bidirectional Connections . . . . . . . . . ..... .... . . ..

Figure 4

: Loop Back . . . . ...... ... . . . . . . .... .. . . . . ..... ..... ..... .... .

Figure 5

: Variable Delay through the matrix with ITDM = 1 . . . . . . . . . ..... .... .

Figure 6

: Variable Delay through the matrix with ITDM = 0 . . . . . . . . . ..... .... .

Figure 7

: Constant Delay through the matrix with SI = 1 . . . . . . . . . . . . . . . . . . . . .

Figure 8

: HDLC and DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .

Figure 9

: Structure of the Receive Circular Queue . . . . . . . . . ..... .... . . ... ..

Figure 10 : Structure of the Transmit Circular Queue . . . . . . . . . ..... .... . . ... ..

Figure 11 : D, C/I and Monitor Channel Path . . . . . . . . . ..... .... . . ... .. . . . . . .

Figure 12 :

Multi-HDLC connected to

µP with multiplexed buses . . . . . . . . . ..... ..

Figure 13 :

Multi-HDLC connected to

µP with non-multiplexed buses . . . . . . . . . . . .

Figure 14 : Microprocessor Interface for INTEL 80C188 . . . . . . .... ..... . . .. . . ..

Figure 15 : Microprocessor Interface for INTEL 80C186 . . . . . . .... ..... . . .. . . ..

Figure 16 : Microprocessor Interface for MOTOROLA 68000 . . . . . . . . . ..... .... .

Figure 17 : Microprocessor Interface for ST9 . . . . . . . . . ..... .... . . ... .. . . . . . .

Figure 18 : 128K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . .

Figure 19 : 512K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . .

Figure 20 : 256K x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . ....

Figure 21 : 1M x 16 DRAM Circuit Organization . . . . . . .... ..... . . .. . . .... . . ..

Figure 22 : 4M x 16 DRAM Circuit Organization . . . . . . .... ..... . . .. . . .... . . ..

Figure 23 : Chain of n

Multi-HDLC Components . . . . . . .... ..... . . .. . . .... . . ..

Figure 24 : MHDLC Clock Generation . . . . .... ...... .... . . ... .. . . . . ..... ...

Figure 25 : VCXO Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . .... ...

Figure 26 : The Three Circular Interrupt Memories . . . . . . . . . . . . . . . . . . . . . . . ....

DC SPECIFICATIONS . .... . . . ... ..... ..... .... . . .. . . .... . . .. . . .... . . ...

CLOCK TIMING . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .

Figure 27 : Clocks received and delivered by the

Multi-HDLC . . . ... . . ... . . ... . .

Figure 28 : Synchronization Signals received by the

Multi-HDLC ... . . .. . . ..... ..

Figure 29 : GCI Synchro Signal delivered by the

Multi-HDLC ... . . .. . . ..... .... .

Figure 30 : V* Synchronization Signal delivered by the

Multi-HDLC . ... . . .... ....

MEMORY TIMING . .... . . . ... ..... ...... .. .. . . . . . .... . . .. . . .... . . ... .. .

Figure 31 : Dynamic Memory Read Signals from the

Multi-HDLC . . . ... . . ... . . ..

Figure 32 : Dynamic Memory Write Signals from the

Multi-HDLC . . . ... . . ... . . ..

Figure 33 : Static Memory Read Signals from the

Multi-HDLC . . . ... . . ... . . ... . .

Figure 34 : Static Memory Write Signals from the

Multi-HDLC . . . ... . . ... . . ... . .

STLC5464

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