STLC5464 datasheet(56/83 Pages) STMICROELECTRONICS

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TSV

: Time Stamping Validated

TSV = 1, the time stamping counter becomes a free binary counter and counts down from 65535

to 0 in step of 250ms (Total = 16384ms). So if an event occurs when the counter indicates A and

if the next event occurs when the counter indicates B then : t = (A-B) x 250ms is the time which

has passedbetweenthe two eventswhich have been stored in memory by the InterruptController

(for Rx C/I and Rx MON CHANNEL only).

TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter

constitute a Watch Dog or a Timer.

EVM

: EXTERNAL VCXO MODE

EVM=1,VCXO Synchronization Counter is divided by 32.

EVM=0,VCXO Synchronization Counter is divided by 30.

: HDLC connected to MATRIX

D7 = 1, the transmit HDLC is connected to matrix input 7, the DIN7 signal is ignored.

D7 = 0, the DIN7 signal is taken into account by the matrix, the transmit HDLC is ignored by the

matrix.

SYN0/1: SYNCHRONIZATION

SYN0/1 : these two bits define the signal applied on FRAMEA/B inputs. For more details, see

”Synchronization signals delivered by the system. 7.1.

SYN1

SYN0

Signal applied on FRAMEA/B inputs

SYIinterface

GCI Interface (the signal defines the first bit of the frame)

Vstar Interface (the signal defines thrid bit of the frame)

Not used

HCL

: HIGH BIT CLOCK

This bit defines the signal applied on CLOCKA/B inputs.

HCL = 1, bit clock signal is at 8192kHz

HCL= 0, bit clock signal is at 4096kHz

CSD

: Clock Supervision Deactivation

CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked.

CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this

disappearance.

SELB : SELECT B

SELB = 1, FRAME B and CLOCK B must be selected.

SELB = 0, FRAME A and CLOCK A must be selected.

BSEL : B SELECTED (this bit is read only)

BSEL = 1, FRAME B and CLOCK B are selected.

BSEL = 0, FRAME A and CLOCK A are selected.

SCL

: Single Clock

This bit defines the signal delivered by DCLK output pin.

SCL = 1, Data Clock is at 2048kHz.

SCL = 0, Data Clock is at 4096kHz.

AFAB : Advanced Frame A/B Signal

AFAB = 1, the advance of Frame A Signal and Frame B Signal is 0.5 bit time versus the signal

frame A (or B) drawn in Figure 27.

AFAB = 0, Frame A Signal and Frame B Signal are in accordance with the clock timing

(see : Synchronization signals delivered by the Figure 27).

VIII - INTERNAL REGISTERS (continued)

STLC5464

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