MPC8377ECVRALDA datasheet(118/124 Pages) FREESCALE

118 / 124 page

MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

118

Freescale Semiconductor

System Design Information

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip

capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the

quick response time necessary. They should also be connected to the power and ground planes through two

vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo

OSCON).

25.3

Connection Recommendations

To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate

signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused

active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins

of the device.

25.4

Output Buffer DC Impedance

The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a

push-pull single-ended driver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD

or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 66). The

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals

OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN)/2.

Figure 66. Driver Impedance Measurement

OVDD

OGND

Pad

Data

SW1

SW2

MPC8377ECVRALDA Datasheet(PDF) 118 Page - Freescale Semiconductor, Inc