MPC8377ECVRALDA datasheet(122/124 Pages) FREESCALE

122 / 124 page

MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

122

Freescale Semiconductor

Document Revision History

27 Document Revision History

Table 86 provides a revision history for this hardware specification.

Table 86. Document Revision History

Revision

Date

Substantive Change(s)

10/2009

• In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.

•In Table 5, “MPC8377E Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.

•In Table 5, “MPC8377E Power Dissipation 1,” added a column for “Typical Application at Tj =65°C (W)”.

•In Table 5, “MPC8377E Power Dissipation 1,” added a column for “Sleep Power at Tj =65°C (W)”.

•In Table 10, removed overbar from CFG_CLKIN_DIV.

•In Table 16, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1

and DDR2 to 600 and 400

μA, respectively. Also, updated Note 1 and added Note 2.

•In Table 19, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to

“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.

•In Table 19, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Table 20, “DDR1 and

DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.

•In Table 28, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.

•In Table 59, Gen 1i/1.5G Receiver AC Specifications,” and Table 61, Gen 2i/3G Receiver AC

Specifications,” corrected titles from “Transmitter” to “Receiver”.

•In Table 71, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V

to VDD pin.

•In Table 73, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”

range to 125–200.

•In Table 78, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.

•In Table 79, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .

•In Section 20.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV,

respectively.

02/2009

• In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two

rows for SerDes. In addition, changed 666 to 667 MHz.

•In Table 5, “MPC8377E Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667

MHz.

•In Table 12, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” Table 20, “DDR1 and

DDR2 SDRAM Output AC Timing Specifications,” and Table 71, “TePBGA II Pinout Listing,” added

footnote to references to MVREF, MDQ, and MDQS, referencing AN3665,

MPC837xE Design Checklist.

•In Table 20, updated tDDKHCX minimum value for 333 MHz to 2.40.

•In Table 71, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified

footnote 10 and added footnote 13.

•In Table 73, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for

core_clk.

•In Table 79, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.

• Updated part numbering information in AF column in Table 83, “Part Numbering Nomenclature.” In

addition, modified extended temperature information in notes 1 and 4.

•In Table 84, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.

12/2008 Initial public release.

MPC8377ECVRALDA Datasheet(PDF) 122 Page - Freescale Semiconductor, Inc

MPC8377ECVRALDA Datasheet(HTML) 122 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL