| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
MPC8569E Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8569E Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc |
|
46 / 127 page ![]() MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 DDR2 and DDR3 SDRAM Controller Freescale Semiconductor 46 2.4.1 DDR2 and DDR3 SDRAM Interface DC Electrical Characteristics The following table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM. The following table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM. Table 13. DDR2 SDRAM Interface DC Electrical Characteristics At recommended operating condition with GVDD =1.8 V 1 Parameter Symbol Min Max Unit Notes I/O reference voltage MVREFn 0.49 × GV DD 0.51 × GV DD V2, 3, 4 Input high voltage VIH MVREFn +0.125 — V 5 Input low voltage VIL — MVREFn – 0.125 V 5 Output high current (VOUT =1.320 V) IOH —–13.4 mA 6, 7 Output low current (VOUT =0.380 V) IOL 13.4 — mA 6, 7 I/O leakage current IOZ –50 50 μA8 Notes: 1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source. 2. MVREFn is expected to be equal to 0.5 × GV DD and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREFn may not exceed the MVREFn DC level by more than ±2% of GVDD (that is, ± 36 mV). 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn +0.04. VTT should track variations in the DC level of MVREFn. 4. The voltage regulator for MVREFn must meet the specifications stated in Table 16. 5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models. 6. IOH and IOL are measured at GVDD = 1.7 V. 7. Refer to the IBIS model for the complete output IV curve characteristics. 8. Output leakage is measured with all outputs disabled, 0 V ≤ V OUT ≤ GVDD. Table 14. DDR3 SDRAM Interface DC Electrical Characteristics At recommended operating condition with GVDD =1.5 V 1 Parameter Symbol Min Max Unit Note I/O reference voltage MVREFn 0.49 × GV DD 0.51 × GV DD V2, 3, 4 |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |