MPC8569E datasheet(83/127 Pages) FREESCALE

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High-Speed SerDes Interfaces (HSSI)

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Figure 42. Single-Ended Reference Clock Input DC Requirements

2.9.2.4

AC Requirements for SerDes Reference Clocks

The following table lists AC requirements for the PCI Express, SGMII, and Serial RapidIO SerDes reference clocks to be

guaranteed by the customer’s application design.

Table 48. SD_REF_CLK and SD_REF_CLK Input Clock Requirements

At recommended operating conditions with ScoreVDD = 1.0 V ± 3%. and 1.1 V ± 3%

Parameter

Symbol

Min

Typ

Max

Unit

Notes

SD_REF_CLK/SD_REF_CLK frequency range

tCLK_REF

—100/125

—

MHz

SD_REF_CLK/SD_REF_CLK clock frequency

tolerance

tCLK_TOL

–350

—

350

ppm

—

SD_REF_CLK/SD_REF_CLK reference clock duty

cycle

tCLK_DUTY

SD_REF_CLK/SD_REF_CLK max deterministic

peak-peak jitter at 10-6 BER

tCLK_DJ

——

SD_REF_CLK/SD_REF_CLK total reference clock

jitter at 10-6 BER (peak-to-peak jitter at refClk input)

tCLK_TJ

—

2, 7

SD_REF_CLK/SD_REF_CLK rising/falling edge rate

tCLKRR/tCLKFR

1—4

V/ns

3, 7

SD_REF_CLK

400 mV < SD_REF_CLK Input Amplitude < 800 mV

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