MPC8569E datasheet(87/127 Pages) FREESCALE

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PCI Express

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.10.3

PCI Express AC Physical Layer Specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.10.3.1

PCI Express AC Physical Layer Transmitter Specifications

This section discusses the PCI Express AC physical layer transmitter specifications for 2.5 Gb/s.

The following table defines the PCI Express (2.5Gb/s) AC specifications for the differential output at all transmitters (TXs).

The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.

DC input

impedance

ZRX-DC

Required RX D+ as well as D– DC impedance

(50 ± 20% tolerance). See Notes 1 and 2.

Powered down

DC input

impedance

ZRX-HIGH-IMP-DC

—

ΚΩ

Required RX D+ as well as D– DC Impedance when

the receiver terminations do not have power. See Note

Electrical idle

detect threshold

VRX-IDLE-DET-

DIFFp-p

—

175

VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–|.

Measured at the package pins of the receiver.

Notes:

1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 46 must be used

as the RX device when taking measurements. If the clocks to the RX and TX are not derived from the same reference clock,

the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

Table 51. PCI Express (2.5Gb/s) Differential Transmitter (TX) Output AC Specifications

At recommended operating conditions with XVDD = 1.0 V ± 3%. and 1.1 V ± 3%

Parameter

Symbol

Min

Typ

Max

Unit

Comments

Unit Interval

399.88

400.00

400.12

Each UI is 400 ps ± 300 ppm. UI does not account

for spread spectrum clock dictated variations. See

Note 1.

Minimum TX eye

width

TTX-EYE

0.70

—

The maximum transmitter jitter can be derived as

TTX-MAX-JITTER = 1 – TTX-EYE = 0.3 UI.

See Notes 2 and 3.

Maximum time

between the jitter

median and

maximum

deviation from the

median

TTX-EYE-MEDIAN-

to-MAX-JITTER

—

0.15

Jitter is defined as the measurement variation of the

crossing points (VTX-DIFFp-p = 0 V) in relation to a

recovered TX UI. A recovered TX UI is calculated

over 3500 consecutive unit intervals of sample data.

Jitter is measured using all edges of the 250

consecutive UI in the center of the 3500 UI used for

calculating the TX UI. See Notes 2 and 3.

Table 50. PCI Express (2.5 Gb/s) Differential Receiver (RX) Input DC Specifications (continued)

At recommended operating conditions with ScoreVDD = 1.0 V ± 3%. and 1.1 V ± 3%

Parameter

Symbol

Min

Typ

Max

Unit

Comments

MPC8569E Datasheet(PDF) 87 Page - Freescale Semiconductor, Inc

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