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MPC8569E Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MPC8569E Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 127 page  MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Ball Layout Diagrams Freescale Semiconductor 8 The following figure provides detailed view D of the MPC8569E 783-pin BGA ball map diagram. Figure 6. MPC8569E Detail D Ball Map GND GND GND GND GND GND GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD GND GND VDD VDD VDD VDD VDD VDD GND GND BVDD IRQ [0] IRQ5_ MSRCID [4] IRQ6_ DVAL XVDD XGND IRQ [3] IRQ [2] SCORE- VDD SCORE- GND GND IRQ [1] Rsvd SD_TX [0] SD_TX [0] SCORE- GND SCORE- VDD SD_RX [0] SD_RX [0] Rsvd Rsvd GND XVDD XGND AGND_ SRDS AVDD_ SRDS SCORE- GND SCORE- VDD GND XVDD XGND SD_TX [1] SD_TX [1] SCORE- GND SCORE- VDD SD_RX [1] SD_RX [1] GND SD_PLL_ TPD SD_IMP_ CAL_RX XGND XVDD SD_REF_ CLK SD_REF_ CLK SCORE- VDD SCORE- GND GND XGND XVDD SD_TX [2] SD_TX [2] SCORE- VDD SCORE- GND SD_RX [2] SD_RX [2] LDP [1] LGPL [5] LGPL1_ LFALE LGPL4_ LUPWAIT_ LBPBSE_ LFRB LGPL0_ LFCLE LGPL3_ LFWP SD_TX_ CLK XVDD XGND SD_IMP_ CAL_TX SD_PLL_ TPA SCORE- GND SCORE- VDD GND LCS [1] BVDD LCS [0] BVDD LA [25] BVDD LCS7_ IRQ [11] XVDD XGND SRESET HRESET_ REQ SCORE- VDD SCORE- GND LCS [2] GND LWE1_ LBS [1] GND LWE0_ LBS0_ LFWE XVDD XGND SD_TX [3] SD_TX [3] XGND SCORE- GND SD_RX [3] SD_RX [3] LA [16] LA [17] LA [19] LA [21] LA [23] LGPL2_ LOE_ LFRE LAD [15] LCS6_ IRQ [10] HRESET DMA_ DACK2_ SD_CMD DMA_ DDONE_ [0] DMA_ DREQ2_ SD_DAT0 DMA_ DACK1_ MSRCID1 LVDD_ VSEL [0] LBCTL LA [20] LA [22] LA [24] LA [26] LAD [13] LAD [12] LA [27] LCS5_ IRQ [9] DMA_ DDONE1_ MSRCID2 DMA_ DREQ1_ MSRCID0 GND OVDD CKSTP_ IN BVDD LCLK [1] BVDD LCLK [0] BVDD LAD [7] BVDD LAD [14] DMA_ DACK_ [0] OVDD DMA_ DDONE2_ SD_WP IIC2_ SCL_SD_ CD UART_ SIN0_DMA _DACK3_ SD_DAT2 CKSTP_ OUT GND LAD [2] GND LAD [6] GND LAD [8] GND LAD [11] DMA_ DREQ_ [0] GND IIC2_ SDA_SD_ CLK IIC1_ SCL UART_ CTS0_DMA _DDONE3_ SD_DAT3 LSYNC_ OUT LSYNC_ IN LAD [3] LAD [4] LAD [5] LALE LAD [9] LAD [10] GND AVDD_ LBIU GND IIC1_ SDA LSSD_ MODE SD_TX_ CLK W Y AA AB AC AD AE AF AG AH R T U V 17 16 15 18 19 20 21 22 23 24 25 26 27 28 DETAIL D UART_ SOUT0_DMA _DREQ3_ SD_DAT1 UART_ RTS [0] |
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