MPC8569E datasheet(63/127 Pages) FREESCALE

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Ethernet Interface

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.6.3.6

TBI Single-Clock Mode AC Specifications

The following table shows the TBI single-clock mode receive AC timing specifications.

The following figure shows the TBI single-clock mode receive AC timing diagram.

Figure 25. TBI Single-Clock Mode Receive AC Timing Diagram

2.6.3.7

RGMII and RTBI AC Timing Specifications

The following table presents the RGMII and RTBI AC timing specifications.

Table 34. TBI Single-Clock Mode Receive AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Typ

Max

Unit

Note

RX_CLK clock period

tTRR

7.5

8.0

8.5

RX_CLK duty cycle

tTRRH

RX_CLK peak-to-peak jitter

tTRRJ

——

250

Rise time RX_CLK (20%–80%)

tTRRR

———

Fall time RX_CLK (80%–20%)

tTRRF

———

RCG[9:0] setup time to RX_CLK rising edge

tTRRDV

2.0

—

RCG[9:0] hold time to RX_CLK rising edge

tTRRDX

1.0

—

Note:

1. The frequency of RX_CLK should not exceed the frequency of gigabit Ethernet reference clock by more than 300 ppm.

2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Table 35. RGMII and RTBI AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Typ

Max

Unit

Notes

Data to clock output skew (at transmitter)

tSKRGT_TX

–500

500

Data to clock input skew (at receiver)

tSKRGT_RX

1.2

—

2.6

Clock period duration

tRGT

7.2

8.0

8.8

Duty cycle for 10BASE-T and 100BASE-TX

tRGTH/tRGT

3, 4, 6

tTRR

tTRRH

tTRRF

tTRRR

RX_CLK

RCG[9:0]

Valid Data

tTRRDX

tTRRDV

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