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AD6623BC/PCB Datasheet(PDF) 33 Page - Analog Devices

No. de pieza AD6623BC/PCB
Descripción Electrónicos  4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
PDF  40 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD6623BC/PCB Datasheet(HTML) 33 Page - Analog Devices

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REV. 0
AD6623
–33–
Channel Function Registers (continued)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
2. Update RCF Mode Select registers
marked with “2”.
3. Ramp Up (if Ramp is enabled)
0x110
15–0
Ch. A RCF Phase EQ Coef1
No Change
0x111
15–0
Ch. A RCF Phase EQ Coef2
No Change
0x112
15–0
Unused
Ch. A RCF FIR–PSK Magnitude 0
0x113
15–0
Unused
Ch. A RCF FIR–PSK Magnitude 1
0x114
15–0
Unused
Ch. A RCF FIR–PSK Magnitude 2
0x115
15–0
Unused
Ch. A RCF FIR–PSK Magnitude 3
0x116
7–6
Unused
Ch. A Serial Data Frame Input Select
0x: Internal Frame Request
10: External SDFI Pad
11: Previous Channel’s Frame End
5
Unused
Ch. A Serial Data Frame Output Select
0: Serial Data Frame Request
1: Serial Data Frame End
4
Unused
Ch. A Serial Clock Slave (SCS)
SCS = 0: Master Mode
(SCLK is an output)
SCS = 1: Slave Mode
(SCLK is an input)
3
Unused
Ch. A Serial Fine Scale Enable
1
2
Unused
Ch. A Serial Time Slot Sync Enable
(ignored in FIR mode)
1
Unused
Ch. A Ramp Interpolation Enable
0
Unused
Ch. A Ramp Enable
0x117
5–0
Unused
Ch. A Mode 0 Ramp Length, R0–1
0x118
4–0
Unused
Ch. A Mode 1 Ramp Length, R1–1
0x119
4–0
Unused
Ch. A Ramp Rest Time, Q
(No inputs requested during rest time.)
0x11A–11F
Unused
No Change
0x120–13F
15–0
Ch. A Data RAM
No Change
0x140–17F
15–14
Unused
No Change
13–0
Unused
Ch. A Ramp RAM
0x180–1FF
15–0
Ch. A Coefficient RAM
No Change
This address is mirrored at 0x900–0x97F
and contiguously extended at 0x980–0x9FF
NOTES
1Clear on
RESET.
2These bits update after a Start or a Beam Sync. See CR 0x10F.
3Allows dynamic updates.
(0x000) Summation Mode Control
Controls features in the summation block of the AD6623.
Bit 5–6:
Reserved.
Bit 4:
Low: Wideband Input Enabled.
High: Wideband Input Disabled.
Bit 3:
Low: Dual Output Disabled.
High: Dual Output Enabled.
Bit 2:
Reserved.
Bit 1:
Low: Output data will be in two’s complement.
High: Output data will be in offset binary.
Bit 0:
Low: Over-range will wrap.
High: Over-range will clip to full scale.
(0x001) Sync Mode Control
Bit 7:
Ignores all but the first pin sync.
Bit 6:
Beam on pin Sync.
Bit 5:
Hop on pin Sync.
Bit 4:
High enables the count down of the Start Hold-Off
Counter. The counter is clocked with the AD6623
CLK signal. When it reaches a count of one the Sleep
bit of the appropriate channel(s) is set low to activate
the channel(s).
Bit 3–0:
High enables synchronization of these channels.
See the Synchronization section of the data sheet for
detailed explanation.
(0x002) BIST Counter
Sets the length, in CLK cycles, of the built-in self test.
(0x003) BIST Result
A read-only register containing the result after a self test. Must be
compared to a known good result for a given setup to determine
pass/fail.



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