AD6623BCSLASHPCB datasheet(19/40 Pages) AD

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AD6623

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Table V. RCF Control Registers

Channel

Bit

Address

Width

Description

0x0A

15–8: NRCF –1 B; 7–0: NRCF –1 A

0x0B

7–0: ORCF

0x0C

9: Ch. A Compact FIR Input Word Length

0: 16 bits–8 I followed by 8 Q

1: 24 bits–12 I followed by 12 Q

8: Ch. A RCF PRBS Enable

7: Ch A RCF PRBS Length

0: 15

1: 8,388,607

6–4: Ch. A RCF Mode Select

000 = FIR

001 = p/4-DQPSK Modulator

010 = GMSK Look-Up Table

011 = MSK Look-Up Table

100 = FIR compact mode

101 = 8-PSK

110 = 3p/8-8PSK Modulator

111 = QPSK Look-Up Table

3–0: Ch. A RCF Taps per Phase

0x0D

7–6: RCF Coarse Scale (g):

00 = 0 dB

01 = –6 dB

10 = –12 dB

11 = –18 dB

5: Ch. A Allpass Ph. Eq. Enable

4–0: Serial Clock Divider (1, ..., 32)

0x0E

15–2: Ch. A Unsigned Scale Factor

1–0: Reserved

0x0F

17–16: Ch. A Time Slot Sync Select

00: Sync0 (See 0x001 Time Slot)

01: Sync1

10: Sync2

11: Sync3

15–0: Ch. A RCF Scale Hold-Off Counter

1) Ramp Down (if Ramp is enabled)

2) Update Scale and Mode

3) Ramp Up (if Ramp is enabled)

0x110

15–0: Ch. A RCF Phase EQ Coef1

0x111

15–0: Ch. A RCF Phase EQ Coef2

0x112

15–0: Ch. A RCF MPSK Magnitude 0

0x113

15–0: Ch. A RCF MPSK Magnitude 1

0x114

15–0: Ch. A RCF MPSK Magnitude 2

0x115

15–0: Ch. A RCF MPSK Magnitude 3

0x116

7: Reserved

6: Ch. A Serial Data Frame Select

0: Serial Data Frame Request

1: Serial Data Frame End

Channel

Bit

Address

Width Description

5: Ch. A External SDFI Select

0: Internal SDFI

1: External SDFI

4: Ch. A SCLK Slave Select

0: Master

1: Slave

3: Ch. A Serial Fine Scale Enable

2: Ch. A Serial Time Slot Sync Enable

(ignored in FIR mode)

1: Ch. A Ramp Interpolation Enable

0: Ch. A Ramp Enable

0x117

5–0: Ch. A Mode 0 Ramp Length, R0–1

0x118

5–0: Ch. A Mode 1 Ramp Length, R1–1

0x119

4–0: Ch. A Ramp Rest Time, Q

0x11A–0x11F

Reserved

0x120–0x13F 16

15–0: Ch. A Data Memory

0x140–0x17F 16

15–14: Reserved

13–0: Ch. A Power Ramp Memory

0x180–0x1FF 16

15–0: Ch. A Coefficient Memory

This address is mirrored at 0x900–0x97F

and contiguously extended at

0x980–0x9FF

PSK MODULATOR

The PSK Modulator is an AD6623 extension feature that is

only available when the control register bit 0x000:7 is high.

The PSK Modulator creates 32-bit complex inputs to the

Interpolating FIR Filter from two or three data bits captured

by the serial port. The FIR Filter operates exactly as if the 32-

bit word came directly from the serial port. There are three

PSK modulation options to choose from: /4-DQPSK, 8-PSK,

and 3 /8-8-PSK. Every symbol of any of these modulations

can be represented by one of the 16 phases shown in Figure 21.

Figure 21. 16-Phase Modulations

AD6623BC/PCB Datasheet(PDF) 19 Page - Analog Devices

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