AD6623BCSLASHPCB datasheet(17/40 Pages) AD

17 / 40 page

REV. 0

AD6623

–17–

9876543210

BIT

< msb, I, lsb >

< msb, Q, lsb >

FIR

9876543210

BIT

< msb, I, lsb >

< msb, Q, lsb >

COMPACT FIR

9876543210

BIT

< msb, I, lsb >

< msb, Q, lsb >

COMPACT FIR

43210

BIT

8PSK

43210

BIT

SERIAL SYNC

QPSK

RAMP

43210

BIT

MSK/GSM

210

BIT

8PSK

BIT

QPSK

BIT

MSK/GSM

Figure 17. Data Formats Supported by the AD6623 when

SCLK Master (SCS = 0), and SFDO Set for Frame Request (SFE = 0)

INTERPOLATING

FIR

FILTER

INTERPOLATING

MSK

MODULATOR

INTERPOLATING

QPSK

MODULATOR

ALLPASS

PHASE

EQUALIZER

PSK

MODULATOR

SCALE

AND

RAMP

DATA FROM SERIAL PORT

DATA TO CIC FILTERS

Figure 18. RCF Block Diagram

Table IV. FIR Filter Internal Precision

Minimum

Maximum

Signal

y Notation

Decimal

Hexadecimal (h)

Decimal

Hexadecimal (h)

I and Q Inputs

1.15

–1.00000

+1.00000

0.999969

0.FFFE

Coefficients

1.15

–1.00000

+1.00000

0.999969

0.FFFE

Product

2.18

–0.99969

+3.00020

1.000000

1.00000

Sum

4.18

–7.00000

+8.0000

7.999996

7.FFFFC

FIR Output

1.17

–1.00000

+1.00000

0.999992

0.FFFF8

The Scale and Ramp block adjusts the final magnitude of the

modulated RCF output. A synchronization pulse from the SYNC0–3

pins or serial words can be used to command this block to ramp

down, pause, and ramp up to a new scale factor. The shape of

the ramp is stored in RAM, allowing complete sample by sample

control at the RCF interpolated rate. This is particularly useful

for time division multiplexed standards such as GSM/EDGE.

Modulator configurations can be updated while the ramp is quiet,

allowing for GSM and EDGE timeslots to be multiplexed together

without resetting or reconfiguring the channel. Each of the RCF

processing blocks is discussed in greater detail in the following

sections.

INTERPOLATING FIR FILTER

The Interpolating FIR Filter realizes a real, sum-of-products filter

on I and Q inputs using a single interleaved Multiply-Accumulator

(MAC) running at the CLK rate. The input signal is interpolated

by integer factors to produce arbitrary impulse responses up to

256 output samples long.

Each bus in the data path carries bipolar two’s complement values.

For the purpose of discussion, we will arbitrarily consider the radix

point positioned so that the input data ranges from –1 to just

below 1. In Figure 19, the data buses are marked x

y to denote

finite precision limitations. A bus marked x

y has x bits above

the radix and y bits below the radix, which implies a range from

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