AD6623BCSLASHPCB datasheet(25/40 Pages) AD

25 / 40 page

REV. 0

AD6623

–25–

frequencies solely by spectral inversion. The digital IF is calcu-

lated using the equation:

NCO

frequency

NCO

=×

(21)

where:

NCO_frequency is the value written to 0xn02,

fIF is the desired intermediate frequency, and

fNCO is fCLK/2 for complex outputs and fCLK for real outputs.

Phase Dither

The AD6623 provides a phase dither option for improving the

spurious performance of the NCO. Phase dither is enabled by

writing a “1” to Bit 3 of Channel Register 0xn01. When phase

dither is enabled, spurs due to phase truncation in the NCO are

randomized. The choice of whether phase dither is used in a system

will ultimately be decided by the system goals and the choice of IF

frequency. The 18 most significant bits of the phase accumulator

are used by the angle to Cartesian conversion. If the NCO frequency

has all zeroes below the 18th bit, then phase dither has no effect.

If the fraction below the 18

th bit is near a 1/2 or 1/3 of the 18th

bit, then spurs will accumulate separated from the IF by 1/2 or

1/3 of the CLK frequency. The smaller the denominator of this

residual fraction, the larger the spurs due to phase truncation will

be. If the phase truncation spurs are unacceptably high for a given

frequency, then the phase dither can reduce these at the penalty

of a slight elevation in total error energy. If the phase truncation

spurs are small, then phase dither will not be effective in reducing

them further, but a slight elevation in total error energy will occur.

Amplitude Dither

Amplitude dither can also be used to improve spurious performance

of the NCO. Amplitude dither is enabled by writing a “1” to Bit 4

of Channel Register at 0xn01. When enabled, amplitude dither

can reduce spurs due to truncation at the input to the QAM. If

the entire frequency word is close to a fraction that has a small

denominator, the spurs due to amplitude truncation will be large

and amplitude dither will spread these spurs effectively. Amplitude

dither also will increase the total error energy by approximately

3 dB. For this reason amplitude dither should be used judiciously.

Phase Offset

The phase offset (Channel Register 0xn04) adds an offset to the

phase accumulator of the NCO. This is a 16-bit register that is

interpreted as a 16-bit unsigned integer. Phase offset ranges

from 0 to nearly 2 radians with a resolution of /32768 radians.

This register allows multiple NCOs to be synchronized to produce

sine waves with a known phase relationship.

NCO Frequency Update and Phase Offset Update Hold-Off

Counters

The update of both the NCO frequency and phase offset

can be synchronized with internal Hold-Off counters. Both of

these counters are 16-bit unsigned integers and are clocked at

the master CLK rate. These Hold-Off counters used in conjunc-

tion with the frequency or phase offset registers, allow beam

forming and frequency hopping. See the Synchronization section

of the data sheet for additional details. The NCO phase can also

be cleared on Sync (set to 0x0000) by setting Bit 2 of Channel

NCO Control Scale

The output of the NCO can be scaled in four steps of 6 dB each

via Channel Register 0xn01, Bits 1–0. Table XV show a break-

down of the NCO Control Scale. The NCO always has loss to

accommodate the possibility that both the I and Q inputs may

reach full-scale simultaneously, resulting in a 3 dB input magnitude.

Table XV. NCO Control Scale

0xn01 Bit 1

0xn01 Bit 0

NCO Output Level

–6 dB (no attenuation)

–12 dB attenuation

–18 dB attenuation

–24 dB attenuation

SUMMATION BLOCK

The Summation Block of the AD6623 serves to combine the

outputs of each channel to create a composite multicarrier signal.

The four channels are summed together and the result is then

added with the 18-bit Wideband Input Bus (IN[17:0]). The final

summation is then driven on the 18-bit Wideband Output Bus

(OUT[17:0]) on the rising edge of the high speed clock. If the

OEN input is high then this output bus is three-stated. If the OEN

input is low then this bus will be driven by the summed data.

The OEN is active high to allow the Wideband Output Bus to

be connected to other busses without using extra logic. Most other

busses (like 374 type registers) require a low output enable, which is

opposite of the AD6623 OEN, thus eliminating extra circuitry.

The wideband parallel input IN[17:0] is defined as bidirectional,

to support dual parallel outputs. Each parallel output produces

the sum of two of the four internal TSPs and AD6623 that can

GEN.

NCO

FREQUENCY

WORD

PHASE

OFFSET

ANGLE TO

CARTESIAN

CONVERSION

GEN.

I DATA FROM

CIC5

Q DATA FROM

CIC5

I, Q

CLK

OFF

MICROPROCESSOR

INTERFACE

Figure 31. Numerically Controlled Oscillator and QAM Mixer

AD6623BC/PCB Datasheet(PDF) 25 Page - Analog Devices

AD6623BC/PCB Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Descarga

Enlace URL