AD7011

REV. B

–7–

PIN FUNCTION DESCRIPTION

SSOP Pin

Number

Mnemonic

Function

POWER SUPPLY

19

Positive power supply for analog section.

Positive power supply for digital section.

14, 18, 23

AGND

Analog ground for transmit section.

6

DGND

Digital ground for transmit section.

ANALOG SIGNAL AND REFERENCE

13

BYPASS

Reference decoupling output. A decoupling capacitor should be connected between this pin and AGND.

16, 17

ITx, ITx

Differential analog outputs for the I channel, representing true and complementary outputs of the I

waveform.

21, 20

QTx, QTx

Differential analog outputs for the Q channel, representing true and complementary outputs of the Q

waveform.

TRANSMIT INTERFACE AND CONTROL

7

MCLK

Master clock, digital input. When operating in Mode 0 (TIA Digital mode), this pin should be driven by a

3.1104 MHz CMOS compatible clock source in digital mode and by 2.56 MHz CMOS compatible clock

source for analog mode.

3

TxCLK

This is a dual function digital input/output. When operating in Mode 0 (TIA Digital mode), this pin is

(FRAME)

configured as a digital output, transmit clock. This may be used to clock in transmit data at 48.6 kHz. When

operating in Mode 1 (analog mode), this pin is configured as a digital input, FRAME. This is used to frame

the clocking in of 16-bit words when bypassing the

π/4 DQPSK modulator and directly loading the I and Q

10-bit DACs.

4

TxDATA

This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this pin is used to

(IDATA)

clock in transmit data on the falling edge of TxCLK at a rate of 48.6 kHz. When operating in Mode 1

(Analog mode), I data is clocked in on the rising edge of MCLK. This data bypasses the

π/4 DQPSK modu-

lator and is loaded into the 10-bit I DAC.

2

BIN (QDATA) This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this input is used to ini-

tiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. When operating in Mode 1

(Analog mode), Q data is clocked in on the rising edge of MCLK. This data bypasses the

π/4 DQPSK modu-

lator and is loaded into the 10-bit Q DAC.

24

BOUT

Burst Out, digital output. This is the BIN input delayed by the pipeline delay, both digital and analog, of the

AD7011. This can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms.

1

POWER

Transmit sleep mode, digital input. When this goes low, the AD7011 goes into sleep mode, drawing minimal

current. When this pin goes high, the AD7011 is brought out of sleep mode and initiates a self-calibration

routine to eliminate the offset between ITx & ITx and the offset between QTx & QTx.

12

READY

Transmit ready, digital output. This output goes high once the self-calibration routine is complete.

9, 11

MODE1,

Mode control, digital inputs. These are used to enter the AD7011 into three different operating modes,

MODE2

see Table I.

8, 10, 15, 22

NC

No Connects. These pins are no connects and should not be used as routes for other circuit signals.