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Functional Description (Continued)

3.2.7

User-defined Dither Patterns

The CS9211 allows the user to define custom dither pat-

terns, should the pre-programmed patterns prove to be

insufficient. As shown in Table 3-13, this memory is

accessed through Offset 424h (control and address) and

428h (data).

The dither RAM structure is 32 columns x 64 rows, in which

each column represents one 8x8 dither pattern matrix, like

oneofthe matrices showninFigure 3-10. Thefirst row of

the 8x8 matrix goes into rows 0 - 7 of the appropriate col-

umn, with the left-most bit going into row 0 or the column,

and the right-most bit going into row 7 of the column. The

second row goes into rows 8-15 of the same column, and

so on until the eighth row of the 8x8 matrix goes into rows

48-63 of the column. This structure is illustrated in Figure

3-11.

Figure 3-11. Dither Ram Structure

The dither RAM is loaded row by row, not column by col-

umn, so the user must write out each matrix in a column,

then convert the resulting rows to the data to be loaded, via

Offset 424h and 428h. Offset 424 points to the row to be

loaded, and offset 428h supplies the data to the row.

Looking back at Figure 3-9, it is apparent that the dither

patterns associated with Cases 1) and 3) are logical

inverses of each other, thereby precluding the need to

store both of them in the RAM. Data is read back from the

dither RAM either inverted or non-inverted, according to

the MSB of the dither bits. If the MSB of the dither bits is

one, data

will be read from the dither RAM as inverted

data. The user who chooses to define custom dither pat-

terns must maintain inverse dither pattern pairs or else

their patterns will not work correctly.

Table 3-12 indicates which 8x8 matrices go into which col-

umns of the dither RAM. The entries in Table 3-12 are a

fractional form of notation employed to identify the matrix.

As showninFigure3-10, the 8x8 matrices aremadeupof

smaller matrices that are replicated to fill out the 8x8

matrix. The notations in Table 3-12 refer to the smaller

matrices (sub-matrices) from which the 8x8 matrices are

built.

The fractional notation in Table 3-12 identifies a smaller

matrix (sub-matrix) by using a denominator which refers to

the number of squares in the sub-matrix, and a numerator

which refers to the number of “1” entries in a given matrix.

Thus the notation “7/8” refers to a 2 x 4 matrix (from the 3-

bit dithering scheme) which contains 7 ones.

Table 3-12 does not contain all possible ‘fractional’ entries

for a given dithering scheme. For instance, in the 3-bit

schemes, there is no entry for the “1/8” matrix. The “1/8”

matrix (being a 2x4 matrix which contains a single 1) would

be the logical inverse of the “7/8” matrix, hence, storing the

1/8 matrix is unnecessary. Similarly, the “2/8” matrix is the

inverse of the “6/8” matrix, and the “3/8” matrix is the

inverse of the “5/8” matrix. The matrices that are not stored

directly are accessed when the most-significant dither bit is

a 1. An exception is the “0/n” matrix, which contains no

ones. It is stored in INVERSE FORM in column 0, since

there is no stored “n/n” matrix to read the inverse of. The “I”

after any fractional designation in the column 0 and 16

entries entries of Table 3-12 indicates this matrix should be

stored in inverse form.

8x8 matrix

01 2

30 31

Columns

543210

Offset 424h (row pointer)

Rows

Dither RAM

Table 3-12. Dither RAM Column Usage

Column

Number of Dither Bits

00/2 I

0/4 I

0/8 I

0/16 I

0/32 I

31/32

15/16

30/32

29/32

7/8

14/16

28/32

27/32

13/16

26/32

25/32

3/4 I

6/8 I

12/16 I

24/32 I

23/32

11/16

22/32

21/32

5/8

10/16

20/32

19/32

9/16

18/32

17/32

1/2

2/4

4/8

8/16

16/32

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