CS9211 datasheet(42/62 Pages) NSC

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Revision 2.1

Offset 404h-407h

Panel Timing Register 2 (R/W)

Reset Value = 00000000h

HIGH_RESOL_

MCLK

High Resolution MCLK: Selects the MCLK frequency in terms or the DOTCLK frequency.

This bit should be programmed as “0” for all the DSTN panels with resolutions up to 800x600, where

the memory clock is the same as the DOTCLK. This should be set to “1” for the 1024x768 DSTN

panel to run the memory clock at two-thirds the rate of the DOTCLK.

0 = Memory clock runs at the same frequency as DOTCLK.

1 = Memory clock runs at two-thirds the frequency of the DOTCLK.

PASS_THRU

Pass-Through: Activates the Pass-Through mode. In Pass-Through mode, the input timing and the

pixel data are passed directly onto the panel interface timing and the panel data pins to drive the

panel; the internal CS9211 logic and timing is not used. In normal mode, Offset 400h[7:0], 404h[29],

and 404h[27:24] are effective.

0 = Normal mode; output timing uses the logic and timing from the CS9211.

1 = Pass-Through mode; CS9211 internal timing logic functions are not used.

LDE_POL_SEL

Display Timing Strobe Polarity Select: Selects the polarity of the LDE pin (pin 32). This can be used

for some TFT panels that require an active low timing LDE.

0 = LDE signal is active low (Default).

1 = LDE signal is active high.

RSVD

Reserved: This bit is not defined.

PSH_CLK_CTL

Panel Shift Clock Retrace Activity Control: Programs the shift clock (SHFCLK, pin 30) to be either

free running or active only during the display period. Some TFT panels recommend keeping the shift

clock running during the retrace time. This bit has no effect in DSTN or SSTN modes.

0 = Shift clock is active only during active display period.

1 = Shift clock is free running during the entire frame period.

LP_HSYNC_SEL

LP/HSYNC Select: Selects the function of LP/HSYNC (pin 31). Set this bit based on the panel type

connected. For DSTN or SSTN panels, set this bit to 0. For TFT panels, set this bit to 1.

0 = LP (output for DSTN/SSTN panel).

1 = HSYNC (output for TFT panel).

LDE_SEL

LDE Select: Always set this bit to 1.

0= Reserved

1 = LDE (output for TFT panel).

FLM_VSYNC_

SEL

FLM/VSYNC Select: Selects function of FLM/VSYNC (pin 33). Set this bit based on the panel type

connected. For DSTN or SSTN panels, set this bit to 0. For TFT panels, set this bit to 1.

0 = FLM (output for DSTN/SSTN panel).

1 = VSYNC (output for TFT panel).

VSYNC_POL

Vertical Sync Output Polarity: Selects positive or negative polarity of the VSYNC output signal (pin

33). This bit is effective only for TFT panels; for this bit to function, bit 24 must be set to 1. Note that

Offset 400h[30] independently controls the polarity of the FP_VSYNC input signal (pin 99).

0 = VSYNC output is active high.

1 = VSYNC output is active low.

HSYNC_POL

Horizontal Sync Output Polarity: Selects polarity of output HSYNC signal (pin 31). This bit is effec-

tive only for TFT panels; for this bit to function, bit 26 must be set to 1. Note that Offset 400h[29]

selects independently controls the polarity of the FP_HSYNC input signal (pin 97).

0 = HSYNC output is active high.

1 = HSYNC output is active low.

21:20

DSTN_TFT

Panel Type Select: Selects panel type. The selection of the panel type in conjunction with the

PIX_OUT (bits [18:16]) setting determines how pixel data is mapped on the output LD/UD pins. This

bit also determines the generation of SHFCLK and other panel timing interface signals.

00 = SSTN/DSTN panel

01 = TFT panel

10 = Reserved

11 = Reserved

COLOR_MONO

Color/Mono Select: Selects color or monochrome LCD panel. 0 = Color; 1 = Monochrome.

Table 4-2. Configuration Registers (Continued)

Bit

Name

Description

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