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CS9211 Datasheet(PDF) 34 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza CS9211
Descripción Electrónicos  Geode CS9211 Graphics Companion Flat Panel Display Controller
PDF  62 Pages
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS9211 Datasheet(HTML) 34 Page - National Semiconductor (TI)

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34
Revision 2.1
Functional Description (Continued)
Table 3-16 provides the mapping for the panel data bits as
inputs to the CRC.
Where:
RU1/BU1/GU1 -> pixel 1
RU2/GU2/BU2 -> pixel 2
andsoonfor theUpper Display from line 1 to line 240ofa
640x480 panel, and
RL1/GL1/BL1 -> pixel 1
RL2/GL2/BL2 -> pixel 2
and so on for the Lower Display from line 241 to line 480.
Panel selection is done through the register bits at Offset
404h[18:16]. The selection of these bits generates the
desired SHFCLK from the pixel clock, based on the panel
type selected, and steers the internal pixel bus onto the
panel interface data pins (the LD and UD groups in Table 3-
4). All unused pins are driven with 0’s.
This panel data is sent to the CRC signature generator.
The CRC value varies for each panel configuration for a
fixed on-screen image.
Table 3-16. Mapping of Panel Data as CRC Input
CRC
Input
(LD/UD)
DSTN 24-Bit, Offset
404h[18:16] = 010
DSTN 16-Bit,
Offset 404h[18:16] = 001
SSTN 8-Bit,
Offset 404h[18:16] = 011
TFT, Offset
404h[18:16] = 010
1st Input
to CRC
2nd Input
to CRC
3rd Input
to CRC
1st Input
to CRC
2nd Input
to CRC
3rd Input
to CRC
bit[0]
BU4
0
0
0
0
0
bit[1]
GU4
0
0
0
0
0
bit[2]
RU4
0
0
0
0
B0
bit[3]
BU3
0
0
0
0
B1
bit4]
GU3
GU3
RU6
BU8
G3
R6
B8
B2
bit[5]
RU3
RU3
BU5
GU8
R3
B5
G8
B3
bit[6]
BU2
BU2
GU5
RU8
B2
G5
R8
B4
bit[7]
GU2
GU2
RU5
BU7
G2
R5
B7
B5
bit[8]
RU2
0
0
0
0
0
bit[9]
BU1
0
0
0
0
0
bit[10]
GU1
RU2
BU4
GU7
R2
B4
G7
G0
bit[11]
RU1
BU1
GU4
RU7
B1
G4
R7
G1
bit[12]
BL4
GU1
RU4
BU6
G1
R4
B6
G2
bit[13]
GL4
RU1
BU3
GU6
R1
B3
G6
G3
bit[14]
RL4
GL3
RL6
BL8
0
G4
bit[15]
BL3
RL3
BL5
GL8
0
G5
bit[16]
GL3
0
0
0
0
0
bit[17]
RL3
0
0
0
0
0
bit[18]
BL2
BL2
GL5
RL8
0
R0
bit[19]
GL2
GL2
RL5
BL7
0
R1
bit[20]
RL2
RL2
BL4
GL7
0
R2
bit[21]
BL1
BL1
GL4
RL7
0
R3
bit[22]
GL1
GL1
RL4
BL6
0
R4
bit[23]
RL1
RL1
BL3
GL6
0
R5



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